\n
address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
Starting Descriptor Address
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Descriptor DWORD 1
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Descriptor DWORD 2
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Descriptor DWORD 3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Current Descriptor DWORD 4
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Channel Configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
enable : PMU Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ll_stopped : Linked List Engine Status
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
manual : Manual Mode Enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
bus_error : AHB Bus Error Interrupt Flag
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
to_stat : AHB Bus Timeout Interrupt Flag
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
to_sel : Time Out Interval Select
bits : 11 - 24 (14 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ps_sel : Time Out Interval Prescale Select
bits : 14 - 29 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
interrupt : Descriptor Interrupt Flag
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
End of enumeration elements list.
int_en : PMU Channel Interrupt Enable
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
End of enumeration elements list.
burst_size : DMA Maximum Burst Size
bits : 24 - 52 (29 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Channel Loop Counters
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
counter_0 : CH1 Loop Counter 1
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
counter_1 : CH1 Loop Counter 0
bits : 16 - 47 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Current Descriptor DWORD 0 (OP)
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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