\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
Pulse Train Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
rate_control : Pulse Train Enable/Rate Control
bits : 0 - 26 (27 bit)
access : read-write
Enumeration:
End of enumeration elements list.
mode : Pulse Train Output Mode/Train Length
bits : 27 - 58 (32 bit)
access : read-write
Enumeration:
0 : 32_BIT
Pulse train, 32 bit pattern.
1 : SQUARE_WAVE
Square wave mode.
2 : 2_BIT
Pulse train, 2 bit pattern.
3 : 3_BIT
Pulse train, 3 bit pattern.
4 : 4_BIT
Pulse train, 4 bit pattern.
5 : 5_BIT
Pulse train, 5 bit pattern.
6 : 6_BIT
Pulse train, 6 bit pattern.
7 : 7_BIT
Pulse train, 7 bit pattern.
8 : 8_BIT
Pulse train, 8 bit pattern.
9 : 9_BIT
Pulse train, 9 bit pattern.
10 : 10_BIT
Pulse train, 10 bit pattern.
11 : 11_BIT
Pulse train, 11 bit pattern.
12 : 12_BIT
Pulse train, 12 bit pattern.
13 : 13_BIT
Pulse train, 13 bit pattern.
14 : 14_BIT
Pulse train, 14 bit pattern.
15 : 15_BIT
Pulse train, 15 bit pattern.
16 : 16_BIT
Pulse train, 16 bit pattern.
17 : 17_BIT
Pulse train, 17 bit pattern.
18 : 18_BIT
Pulse train, 18 bit pattern.
19 : 19_BIT
Pulse train, 19 bit pattern.
20 : 20_BIT
Pulse train, 20 bit pattern.
21 : 21_BIT
Pulse train, 21 bit pattern.
22 : 22_BIT
Pulse train, 22 bit pattern.
23 : 23_BIT
Pulse train, 23 bit pattern.
24 : 24_BIT
Pulse train, 24 bit pattern.
25 : 25_BIT
Pulse train, 25 bit pattern.
26 : 26_BIT
Pulse train, 26 bit pattern.
27 : 27_BIT
Pulse train, 27 bit pattern.
28 : 28_BIT
Pulse train, 28 bit pattern.
29 : 29_BIT
Pulse train, 29 bit pattern.
30 : 30_BIT
Pulse train, 30 bit pattern.
31 : 31_BIT
Pulse train, 31 bit pattern.
End of enumeration elements list.
Pulse Train Output Pattern
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Pulse Train Loop Count
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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