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ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

LIMIT0

LIMIT1

LIMIT2

LIMIT3

AFE_CTRL

RO_CAL0

RO_CAL1

RO_CAL2

STATUS

DATA

INTR


CTRL

ADC Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cpu_adc_start adc_pu buf_pu adc_refbuf_pu adc_chgpump_pu buf_chop_dis buf_pump_dis buf_bypass adc_refscl adc_scale adc_refsel adc_clk_en adc_chsel adc_xref adc_dataalign afe_pwr_up_dly

cpu_adc_start : Start ADC Conversion
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_pu : ADC Power Up
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

buf_pu : ADC Input Buffer Power Up
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_refbuf_pu : ADC Reference Buffer Power Up
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_chgpump_pu : ADC Charge Pump Power Up
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

buf_chop_dis : ADC Input Buffer Chop Disable (INTERNAL ONLY)
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

buf_pump_dis : Disable Use of Charge Pump Output by Input Buffer (INTERNAL)
bits : 6 - 12 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

buf_bypass : Bypass Input Buffer
bits : 7 - 14 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_refscl : ADC Reference Scale
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_scale : ADC Scale
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_refsel : ADC Reference (VRef) Select (INTERNAL ONLY)
bits : 10 - 20 (11 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_clk_en : ADC Clock Enable
bits : 11 - 22 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_chsel : ADC Channel Select
bits : 12 - 27 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_xref : Enable Use of ADC External Reference
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_dataalign : ADC Data Alignment Select
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

End of enumeration elements list.

afe_pwr_up_dly : Delay from ADC Powerup Until ADC Ready Asserted
bits : 24 - 55 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


LIMIT0

ADC Limit
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT0 LIMIT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.


LIMIT1

ADC Limit 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT1 LIMIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.


LIMIT2

ADC Limit 2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT2 LIMIT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.


LIMIT3

ADC Limit 3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT3 LIMIT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.


AFE_CTRL

AFE Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFE_CTRL AFE_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tmon_intbias_en tmon_extbias_en

tmon_intbias_en : Enable internal temperature measurement bias generator
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

tmon_extbias_en : Enable external temperature measurement bias generator
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.


RO_CAL0

RO Trim Calibration Register 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RO_CAL0 RO_CAL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ro_cal_en ro_cal_run ro_cal_load ro_cal_atomic dummy trm_mu ro_trm

ro_cal_en : RO Calibration Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ro_cal_run : RO Calibration Run
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ro_cal_load : RO Calibration Load Initial Value
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ro_cal_atomic : RO Calibration Run Atomic
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

dummy : Dummy Write Field
bits : 5 - 12 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

trm_mu : RO Trim Adaptation Gain
bits : 8 - 27 (20 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ro_trm : RO Trim Calibration Result
bits : 23 - 54 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


RO_CAL1

RO Trim Calibration Register 1
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RO_CAL1 RO_CAL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 trm_init trm_min trm_max

trm_init : RO Trim Initial Value
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

trm_min : RO Trim Maximum Adaptive Limit
bits : 10 - 28 (19 bit)
access : read-write

Enumeration:

End of enumeration elements list.

trm_max : RO Trim Minimum Adaptive Limit
bits : 20 - 48 (29 bit)
access : read-write

Enumeration:

End of enumeration elements list.


RO_CAL2

RO Trim Calibration Register 2
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RO_CAL2 RO_CAL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 auto_cal_done_cnt

auto_cal_done_cnt : Auto Cal Time Delay for Atomic Calibration (in milliseconds)
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.


STATUS

ADC Status
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc_active ro_cal_atomic_active afe_pwr_up_active adc_overflow

adc_active : ADC Conversion In Progress
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ro_cal_atomic_active : RO Frequency Calibration Active (If Atomic)
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

afe_pwr_up_active : AFE Power Up Delay Active
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

adc_overflow : ADC Overflow
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.


DATA

ADC Output Data
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc_data

adc_data : ADC Converted Sample Data Output
bits : 0 - 15 (16 bit)
access : read-only

Enumeration:

End of enumeration elements list.


INTR

ADC Interrupt Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc_done_ie adc_ref_ready_ie adc_hi_limit_ie adc_lo_limit_ie adc_overflow_ie ro_cal_done_ie adc_done_if adc_ref_ready_if adc_hi_limit_if adc_lo_limit_if adc_overflow_if ro_cal_done_if adc_int_pending

adc_done_ie : ADC Done Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_ref_ready_ie : ADC Reference Ready Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_hi_limit_ie : ADC Hi Limit Monitor Interrupt Enable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_lo_limit_ie : ADC Lo Limit Monitor Interrupt Enable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_overflow_ie : ADC Overflow Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ro_cal_done_ie : RO Cal Done Interrupt Enable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_done_if : ADC Done Interrupt Flag
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_ref_ready_if : ADC Reference Ready Interrupt Flag
bits : 17 - 34 (18 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_hi_limit_if : ADC Hi Limit Monitor Interrupt Flag
bits : 18 - 36 (19 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_lo_limit_if : ADC Lo Limit Monitor Interrupt Flag
bits : 19 - 38 (20 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_overflow_if : ADC Overflow Interrupt Flag
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ro_cal_done_if : RO Cal Done Interrupt Flag
bits : 21 - 42 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.

adc_int_pending : ADC Interrupt Pending Status
bits : 22 - 44 (23 bit)
access : read-only

Enumeration:

End of enumeration elements list.



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