Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SPI Slave General Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spi_slave_en : SPI Slave Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration: Enable ( read-write )
0 : Disabled
Disable SPI Slave
1 : Enabled
Enable SPI Slave
End of enumeration elements list.
tx_fifo_en : TX FIFO Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration: Enable ( read-write )
0 : Disabled
Disable SPI Slave TX FIFO
1 : Enabled
Enable SPI Slave TX FIFO
End of enumeration elements list.
rx_fifo_en : SPI RX FIFO Enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration: Enable ( read-write )
0 : Disabled
Disable SPI Slave RX FIFO
1 : Enabled
Enable SPI Slave RX FIFO
End of enumeration elements list.
data_width : Width of SPI Slave Data Transfers
bits : 4 - 9 (6 bit)
access : read-write
Enumeration: Enable ( read-write )
0 : x1
1-bit Wide
1 : x2
2-bit Wide/Dual
2 : x4
4-bit Wide/Quad
3 : invalid
Reserved for future use. Do not use.
End of enumeration elements list.
spi_mode : Defines Clock Polarity (bit 17) and Clock Phase (bit 16), collectively referred to as SPI Mode.
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_clk_invert : Invert TX Clock
bits : 20 - 40 (21 bit)
access : read-write
Enumeration: Enable ( read-write )
0 : no_effect
No Effect
1 : Invert
Inverts the TX transmit clock such that outgoing data is updated on the opposite clock edge from that specified by spi_mode. Effectively, this inverts the value of the Clock Polarity bit from the value specified in spi_mode.
End of enumeration elements list.
disable_parking : Disable automatic resetting of SPI Slave on exit from LP Modes
bits : 31 - 62 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPI Slave Interrupt Enable/Disable Settings
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_fifo_ae : TX FIFO Almost Empty Int Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : disabled
Disable Interrupt
1 : enabled
Enable Interrupt
End of enumeration elements list.
rx_fifo_af : RX FIFO Almost Full Int Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0 : disabled
Disable Interrupt
1 : enabled
Enable Interrupt
End of enumeration elements list.
tx_no_data : No Data in TX FIFO Int Enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : disabled
Disable Interrupt
1 : enabled
Enable Interrupt
End of enumeration elements list.
rx_lost_data : RX FIFO Overflow Int Enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : disabled
Disable Interrupt
1 : enabled
Enable Interrupt
End of enumeration elements list.
tx_underflow : TX Underflow Int Enable
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
0 : disabled
Disable Interrupt
1 : enabled
Enable Interrupt
End of enumeration elements list.
ss_asserted : Slave Select Asserted Int Enable
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
0 : disabled
Disable Interrupt
1 : enabled
Enable Interrupt
End of enumeration elements list.
ss_deasserted : Slave Select Deasserted Int Enable
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
0 : disabled
Disable Interrupt
1 : enabled
Enable Interrupt
End of enumeration elements list.
SPI Master FIFO Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_fifo_ae_lvl : Transaction FIFO Almost Empty Flag Level
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_af_lvl : Receive FIFO Almost Full Flag Level
bits : 8 - 20 (13 bit)
access : read-only
Enumeration:
End of enumeration elements list.
SPI Slave FIFO Status Information
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_fifo_used : Number of Bytes in Transmit FIFO
bits : 0 - 5 (6 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rx_fifo_used : Number of Bytes in Receive FIFO
bits : 8 - 21 (14 bit)
access : read-only
Enumeration:
End of enumeration elements list.
SPI Slave Interrupt Flags
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_fifo_ae : TX FIFO Almost Empty
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_af : RX FIFO Almost Full
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_no_data : TX FIFO Empty
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_lost_data : RX FIFO Overflow
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss_asserted : Slave Select Asserted
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss_deasserted : Slave Select Deasserted
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
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