\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
System Clock Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
crypto_enable : Cryptographic (TPU) Relaxation Oscillator Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
crypto_stability_count : Crypto Oscillator Stability Select
bits : 4 - 11 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Trim Calculation Controls
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
trim_clk_sel : Trim Clock Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
trim_calc_start : Start Trim Calculation
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
trim_calc_completed : Trim Calculation Completed
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
End of enumeration elements list.
trim_enable : Trim Logic Enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
trim_calc_results : Trim Calculation Results
bits : 16 - 41 (26 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Control Settings for Crypto Clock 0 - AES
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
aes_clk_scale : Control Settings for Crypto Clock 0 - AES
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for Crypto Clock 1 - MAA
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
maa_clk_scale : Control Settings for Crypto Clock 1 - MAA
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for Crypto Clock 2 - PRNG
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
prng_clk_scale : Control Settings for Crypto Clock 2 - PRNG
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
I2C Timer Control
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
i2c_1ms_timer_en : I2C 1ms Timer Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Dynamic Clock Gating Control Register 0
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
cm4_clk_gater : Clock Gating Control for CM4 CPU
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ahb32_clk_gater : Clock Gating Control for AHB32
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
icache_clk_gater : Clock Gating Control for Instruction Cache
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
flash_clk_gater : Clock Gating Control for Flash Memory
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
sram_clk_gater : Clock Gating Control for SRAM
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
apb_bridge_clk_gater : Clock Gating Control for AHB-to-APB Bridge
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
End of enumeration elements list.
sysman_clk_gater : Clock Gating Control for CLKMAN, PWRMAN, and IOMAN
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ptp_clk_gater : Clock Gating Control for PTP Logic
bits : 14 - 29 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ssb_mux_clk_gater : Clock Gating Control for SSB Mux
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
End of enumeration elements list.
pad_clk_gater : Clock Gating Control for Pad Mode Filter
bits : 18 - 37 (20 bit)
access : read-write
Enumeration:
End of enumeration elements list.
spix_clk_gater : Clock Gating Control for SPI XIP
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
End of enumeration elements list.
pmu_clk_gater : Clock Gating Control for PMU
bits : 22 - 45 (24 bit)
access : read-write
Enumeration:
End of enumeration elements list.
usb_clk_gater : Clock Gating Control for USB
bits : 24 - 49 (26 bit)
access : read-write
Enumeration:
End of enumeration elements list.
crc_clk_gater : Clock Gating Control for CRC
bits : 26 - 53 (28 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tpu_clk_gater : Clock Gating Control for TPU
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
End of enumeration elements list.
watchdog0_clk_gater : Clock Gating Control for Watchdog Timer 0
bits : 30 - 61 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Dynamic Clock Gating Control Register 1
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
watchdog1_clk_gater : Clock Gating Control for Watchdog Timer 1
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
gpio_clk_gater : Clock Gating Control for GPIO Ports
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
timer0_clk_gater : Clock Gating Control for Timer/Counter Module 0
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
timer1_clk_gater : Clock Gating Control for Timer/Counter Module 1
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
timer2_clk_gater : Clock Gating Control for Timer/Counter Module 2
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
timer3_clk_gater : Clock Gating Control for Timer/Counter Module 3
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
End of enumeration elements list.
timer4_clk_gater : Clock Gating Control for Timer/Counter Module 4
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
End of enumeration elements list.
timer5_clk_gater : Clock Gating Control for Timer/Counter Module 5
bits : 14 - 29 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
pulsetrain_clk_gater : Clock Gating Control for Pulse Train Generators
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
End of enumeration elements list.
uart0_clk_gater : Clock Gating Control for UART 0
bits : 18 - 37 (20 bit)
access : read-write
Enumeration:
End of enumeration elements list.
uart1_clk_gater : Clock Gating Control for UART 1
bits : 20 - 41 (22 bit)
access : read-write
Enumeration:
End of enumeration elements list.
uart2_clk_gater : Clock Gating Control for UART 2
bits : 22 - 45 (24 bit)
access : read-write
Enumeration:
End of enumeration elements list.
uart3_clk_gater : Clock Gating Control for UART 3
bits : 24 - 49 (26 bit)
access : read-write
Enumeration:
End of enumeration elements list.
i2cm0_clk_gater : Clock Gating Control for I2C Master 0
bits : 26 - 53 (28 bit)
access : read-write
Enumeration:
End of enumeration elements list.
i2cm1_clk_gater : Clock Gating Control for I2C Master 1
bits : 28 - 57 (30 bit)
access : read-write
Enumeration:
End of enumeration elements list.
i2cm2_clk_gater : Clock Gating Control for I2C Master 2
bits : 30 - 61 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Dynamic Clock Gating Control Register 2
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
i2cs_clk_gater : Clock Gating Control for I2C Slave
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
spi0_clk_gater : Clock Gating Control for SPI Master 0
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
spi1_clk_gater : Clock Gating Control for SPI Master 1
bits : 4 - 9 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
spi2_clk_gater : Clock Gating Control for SPI Master 2
bits : 6 - 13 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
spi_bridge_clk_gater : Clock Gating Control for SPI Bridge
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
owm_clk_gater : Clock Gating Control for 1-Wire Master (OWM)
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
End of enumeration elements list.
adc_clk_gater : Clock Gating Control for ADC
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
End of enumeration elements list.
spis_clk_gater : Clock Gating Control for SPI Slave
bits : 14 - 29 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CM4 Start Clock on Interrupt Enable 0
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ints : Interrupt Sources 0-31
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CM4 Start Clock on Interrupt Enable 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ints : Interrupt Sources 32-63
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
CM4 Start Clock on Interrupt Enable 2
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ints : Interrupt Sources 95-64
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
System Clock Controls
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
system_source_select : System Clock Source Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
usb_clock_enable : USB Clock Enable
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
usb_clock_select : USB Clock Select
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
crypto_clock_enable : Crypto Clock Enable
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rtos_mode : Enable RTOS Mode for SysTick Timers
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cpu_dynamic_clock : Enable CPU Dynamic Clock Gating
bits : 13 - 26 (14 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wdt0_clock_enable : Watchdog 0 Clock Enable
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wdt0_clock_select : Watchdog 0 Clock Source Select
bits : 17 - 35 (19 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wdt1_clock_enable : Watchdog 1 Clock Enable
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wdt1_clock_select : Watchdog 1 Clock Source Select
bits : 21 - 43 (23 bit)
access : read-write
Enumeration:
End of enumeration elements list.
adc_clock_enable : ADC Clock Enable
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK0 - Cortex M4 Clock
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
cm4_clk_scale : Control Settings for CLK0 - Cortex M4 Clock
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK1 - Synchronizer Clock
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
sync_clk_scale : Control Settings for CLK1 - Synchronizer Clock
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK2 - SPI XIP Clock
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spix_clk_scale : Control Settings for CLK2 - SPI XIP Clock
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK3 - PRNG Clock
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
prng_clk_scale : Control Settings for CLK3 - PRNG Clock
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK4 - Watchdog Timer 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
watchdog0_clk_scale : Control Settings for CLK4 - Watchdog Timer 0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK5 - Watchdog Timer 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
watchdog1_clk_scale : Control Settings for CLK5 - Watchdog Timer 1
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK6 - Clock for GPIO Ports
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
gpio_clk_scale : Control Settings for CLK6 - Clock for GPIO Ports
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK7 - Source Clock for All Pulse Trains
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
pulse_train_clk_scale : Control Settings for CLK7 - Source Clock for All Pulse Trains
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK8 - Source Clock for All UARTs
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
uart_clk_scale : Control Settings for CLK8 - Source Clock for All UARTs
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK9 - Source Clock for All I2C Masters
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
i2cm_clk_scale : Control Settings for CLK9 - Source Clock for All I2C Masters
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK10 - Source Clock for I2C Slave
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
i2cs_clk_scale : Control Settings for CLK10 - Source Clock for I2C Slave
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK11 - SPI Master 0
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spi0_clk_scale : Control Settings for CLK11 - SPI Master 0
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK12 - SPI Master 1
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spi1_clk_scale : Control Settings for CLK12 - SPI Master 1
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK13 - SPI Master 2
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spi2_clk_scale : Control Settings for CLK13 - SPI Master 2
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK14 - SPI Bridge Clock
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spib_clk_scale : Control Settings for CLK14 - SPI Bridge Clock
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK15 - 1-Wire Master Clock
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
owm_clk_scale : Control Settings for CLK15 - 1-Wire Master Clock
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Interrupt Flags
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
crypto_stable : Crypto Oscillator Stable Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
sys_ro_stable : System Oscillator Stable Interrupt Flag
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Control Settings for CLK16 - SPI Slave Clock
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spis_clk_scale : Control Settings for CLK16 - SPI Slave Clock
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Interrupt Enable/Disable Controls
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
crypto_stable : Crypto Oscillator Stable Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
sys_ro_stable : System Oscillator Stable Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
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