\n

FLC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FADDR

USER_OPTION

CTRL2

INTFL1

INTEN1

BL_CTRL

TWK_CYCL_CNT

PDM33

SLM

DISABLE_XR0

DISABLE_XR1

DISABLE_XR2

DISABLE_XR3

DISABLE_XR4

DISABLE_XR5

DISABLE_XR6

DISABLE_XR7

INTR

FDATA

DISABLE_WE0

DISABLE_WE1

DISABLE_WE2

DISABLE_WE3

DISABLE_WE4

DISABLE_WE5

DISABLE_WE6

DISABLE_WE7

FCKDIV

PERFORM

TACC

TPROG

CTRL

STATUS

SECURITY

BYPASS


FADDR

Flash Operation Address
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FADDR FADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 faddr

faddr : Flash Operation Address
bits : 0 - 21 (22 bit)
access : read-write

Enumeration:

End of enumeration elements list.


USER_OPTION

Used to set DSB Access code and Auto-Lock in info block
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER_OPTION USER_OPTION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CTRL2

Flash Control Register 2
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 flash_lve bypass_ahb_fail

flash_lve : Flash LVE Enable
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

bypass_ahb_fail : AHB Fail Bypass
bits : 8 - 23 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.


INTFL1

Interrupt Flags Register 1
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFL1 INTFL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sram_addr_wrapped invalid_flash_addr flash_read_locked trim_update_done flc_state_done flc_prog_complete

sram_addr_wrapped : SRAM Address Wrapped Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

invalid_flash_addr : Invalid Flash Address Interrupt Flag
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flash_read_locked : Flash Read from Locked Area Interrupt Flag
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

trim_update_done : Trim Update Complete Interrupt Flag
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flc_state_done : FLC State Machine Reached DONE Interrupt Flag
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flc_prog_complete : Program (Write or Erase) Operation Completed Interrupt Flag
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.


INTEN1

Interrupt Enable/Disable Register 1
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN1 INTEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 sram_addr_wrapped invalid_flash_addr flash_read_locked trim_update_done flc_state_done flc_prog_complete

sram_addr_wrapped : SRAM Address Wrapped Interrupt Enable/Disable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

invalid_flash_addr : Invalid Flash Address Interrupt Enable/Disable
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flash_read_locked : Flash Read from Locked Area Interrupt Enable/Disable
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

trim_update_done : Trim Update Complete Interrupt Enable/Disable
bits : 3 - 6 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flc_state_done : FLC State Machine Reached DONE Interrupt Enable/Disable
bits : 4 - 8 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flc_prog_complete : Program (Write or Erase) Op Completed Int Enable/Disable
bits : 5 - 10 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.


BL_CTRL

Bootloader Control Register
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BL_CTRL BL_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TWK_CYCL_CNT

Cycle Count Tweak Register
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWK_CYCL_CNT TWK_CYCL_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PDM33

PDM33 Register
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDM33 PDM33 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SLM

Sleep Mode Register
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLM SLM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_XR0

Disable Flash Page Exec/Read Register 0
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_XR0 DISABLE_XR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_XR1

Disable Flash Page Exec/Read Register 1
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_XR1 DISABLE_XR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_XR2

Disable Flash Page Exec/Read Register 2
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_XR2 DISABLE_XR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_XR3

Disable Flash Page Exec/Read Register 3
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_XR3 DISABLE_XR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_XR4

Disable Flash Page Exec/Read Register 4
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_XR4 DISABLE_XR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_XR5

Disable Flash Page Exec/Read Register 5
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_XR5 DISABLE_XR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_XR6

Disable Flash Page Exec/Read Register 6
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_XR6 DISABLE_XR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_XR7

Disable Flash Page Exec/Read Register 7
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_XR7 DISABLE_XR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INTR

Flash Controller Interrupt Flags and Enable/Disable 0
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 finished_if failed_if finished_ie failed_ie fail_flags

finished_if : Flash Write/Erase Operation Finished
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

failed_if : Flash Operation Failed
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

finished_ie : Flash Write/Erase Operation Finished Interrupt Enable
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

failed_ie : Flash Operation Failed Interrupt Enable
bits : 9 - 18 (10 bit)
access : read-write

Enumeration:

End of enumeration elements list.

fail_flags : Flash Operation Failure Details
bits : 16 - 47 (32 bit)
access : read-only

Enumeration:

End of enumeration elements list.


FDATA

Flash Operation Data Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FDATA FDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_WE0

Disable Flash Page Write/Erase Register 0
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_WE0 DISABLE_WE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_WE1

Disable Flash Page Write/Erase Register 1
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_WE1 DISABLE_WE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_WE2

Disable Flash Page Write/Erase Register 2
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_WE2 DISABLE_WE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_WE3

Disable Flash Page Write/Erase Register 3
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_WE3 DISABLE_WE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_WE4

Disable Flash Page Write/Erase Register 4
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_WE4 DISABLE_WE4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_WE5

Disable Flash Page Write/Erase Register 5
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_WE5 DISABLE_WE5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_WE6

Disable Flash Page Write/Erase Register 6
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_WE6 DISABLE_WE6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DISABLE_WE7

Disable Flash Page Write/Erase Register 7
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISABLE_WE7 DISABLE_WE7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FCKDIV

Flash Clock Pulse Divisor
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCKDIV FCKDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fckdiv auto_fckdiv_result

fckdiv : Flash Clock Pulse Divisor
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

auto_fckdiv_result : Auto FCKDIV Calculation Result
bits : 16 - 47 (32 bit)
access : read-only

Enumeration:

End of enumeration elements list.


PERFORM

Flash Performance Settings
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERFORM PERFORM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 delay_se_en fast_read_mode_en en_prevent_fail en_back2back_rds en_back2back_wrs en_merge_grab_gnt auto_tacc auto_clkdiv

delay_se_en : Delay SE Enable (Deprecated)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

fast_read_mode_en : Fast Read Mode Enable (Deprecated)
bits : 8 - 16 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

en_prevent_fail : Prevent Fail Flag Set on FLC Busy
bits : 12 - 24 (13 bit)
access : read-write

Enumeration:

End of enumeration elements list.

en_back2back_rds : Enable Back To Back Reads
bits : 16 - 32 (17 bit)
access : read-write

Enumeration:

End of enumeration elements list.

en_back2back_wrs : Enable Back To Back Writes
bits : 20 - 40 (21 bit)
access : read-write

Enumeration:

End of enumeration elements list.

en_merge_grab_gnt : Enable Merge Grab GNT
bits : 24 - 48 (25 bit)
access : read-write

Enumeration:

End of enumeration elements list.

auto_tacc : Auto TACC
bits : 28 - 56 (29 bit)
access : read-write

Enumeration:

End of enumeration elements list.

auto_clkdiv : Auto CLKDIV
bits : 29 - 58 (30 bit)
access : read-write

Enumeration:

End of enumeration elements list.


TACC

Flash Read Cycle Config
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TACC TACC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TPROG

Flash Write Cycle Config
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPROG TPROG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CTRL

Flash Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 write mass_erase page_erase erase_code info_block_unlock write_enable pending info_block_valid auto_incre_mode flsh_unlock

write : Start Flash Write Operation
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

mass_erase : Start Flash Mass Erase Operation
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

page_erase : Start Flash Page Erase Operation
bits : 2 - 4 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

erase_code : Flash Erase Code
bits : 8 - 23 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

info_block_unlock : Flash Info Block Locked
bits : 16 - 32 (17 bit)
access : read-only

Enumeration:

End of enumeration elements list.

write_enable : Flash Writes Enabled
bits : 17 - 34 (18 bit)
access : read-only

Enumeration:

End of enumeration elements list.

pending : Flash Controller Status
bits : 24 - 48 (25 bit)
access : read-only

Enumeration:

End of enumeration elements list.

info_block_valid : Info Block Valid Status
bits : 25 - 50 (26 bit)
access : read-only

Enumeration:

End of enumeration elements list.

auto_incre_mode : Address Auto-Increment Mode
bits : 27 - 54 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flsh_unlock : Flash Write/Erase Enable
bits : 28 - 59 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


STATUS

Security Status Flags
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 jtag_lock_window jtag_lock_static auto_lock trim_update_done info_block_valid

jtag_lock_window : Debug Locked - Hardware Window
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

jtag_lock_static : Debug Locked - Firmware Lockout
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

auto_lock : Debug Locked - Auto Lock
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.

trim_update_done : Trim Update Done
bits : 29 - 58 (30 bit)
access : read-only

Enumeration:

End of enumeration elements list.

info_block_valid : Info Block Valid
bits : 30 - 60 (31 bit)
access : read-only

Enumeration:

End of enumeration elements list.


SECURITY

Flash Controller Security Settings
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECURITY SECURITY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 debug_disable mass_erase_lock disable_ahb_wr flc_settings_lock security_lock

debug_disable : Debug Lockout
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

mass_erase_lock : Mass Erase Lockout
bits : 8 - 19 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

disable_ahb_wr : Disable AHB Flash Write Operations
bits : 16 - 35 (20 bit)
access : read-write

Enumeration:

End of enumeration elements list.

flc_settings_lock : FLC Settings Lock
bits : 24 - 51 (28 bit)
access : read-write

Enumeration:

End of enumeration elements list.

security_lock : Security Lock
bits : 28 - 59 (32 bit)
access : read-write

Enumeration:

End of enumeration elements list.


BYPASS

Status Flags for DSB Operations
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BYPASS BYPASS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 destruct_bypass_erase superwipe_erase destruct_bypass_complete superwipe_complete

destruct_bypass_erase : Destructive Security Bypass In Progress
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

superwipe_erase : Superwipe Erase In Progress
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

destruct_bypass_complete : Destructive Security Bypass Erase Complete
bits : 2 - 4 (3 bit)
access : read-only

Enumeration:

End of enumeration elements list.

superwipe_complete : Superwipe Erase Complete
bits : 3 - 6 (4 bit)
access : read-only

Enumeration:

End of enumeration elements list.



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