\n

ADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL

LIMIT0

LIMIT1

LIMIT2

LIMIT3

LIMIT[0]

LIMIT[1]

STATUS

LIMIT[2]

LIMIT[3]

DATA

INTR


CTRL

ADC Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 start pwr refbuf_pwr chgpump_pwr ref_scale scale ref_sel clk_en ch_sel adc_xref data_align

start : Start ADC Conversion
bits : 0 - 0 (1 bit)
access : read-write

pwr : ADC Power Up
bits : 1 - 2 (2 bit)
access : read-write

refbuf_pwr : ADC Reference Buffer Power Up
bits : 3 - 6 (4 bit)
access : read-write

chgpump_pwr : ADC Charge Pump Power Up
bits : 4 - 8 (5 bit)
access : read-write

ref_scale : ADC Reference Scale
bits : 8 - 16 (9 bit)
access : read-write

scale : ADC Scale
bits : 9 - 18 (10 bit)
access : read-write

ref_sel : ADC Reference (VRef) Select (INTERNAL ONLY)
bits : 10 - 20 (11 bit)
access : read-write

clk_en : ADC Clock Enable
bits : 11 - 22 (12 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 12 - 27 (16 bit)
access : read-write

adc_xref : Enable Use of ADC External Reference
bits : 16 - 32 (17 bit)
access : read-write

data_align : ADC Data Alignment Select
bits : 17 - 34 (18 bit)
access : read-write


LIMIT0

ADC Limit
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT0 LIMIT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write


LIMIT1

ADC Limit
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT1 LIMIT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write


LIMIT2

ADC Limit
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT2 LIMIT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write


LIMIT3

ADC Limit
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT3 LIMIT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write


LIMIT[0]

ADC Limit
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT[0] LIMIT[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write


LIMIT[1]

ADC Limit
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT[1] LIMIT[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write


STATUS

ADC Status
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 active afe_pwr_up_active overflow

active : ADC Conversion In Progress
bits : 0 - 0 (1 bit)
access : read-only

afe_pwr_up_active : AFE Power Up Delay Active
bits : 2 - 4 (3 bit)
access : read-only

overflow : ADC Overflow
bits : 3 - 6 (4 bit)
access : read-only


LIMIT[2]

ADC Limit
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT[2] LIMIT[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write


LIMIT[3]

ADC Limit
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIMIT[3] LIMIT[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch_lo_limit ch_hi_limit ch_sel ch_lo_limit_en ch_hi_limit_en

ch_lo_limit : Low Limit Threshold
bits : 0 - 9 (10 bit)
access : read-write

ch_hi_limit : High Limit Threshold
bits : 12 - 33 (22 bit)
access : read-write

ch_sel : ADC Channel Select
bits : 24 - 51 (28 bit)
access : read-write

ch_lo_limit_en : Low Limit Monitoring Enable
bits : 28 - 56 (29 bit)
access : read-write

ch_hi_limit_en : High Limit Monitoring Enable
bits : 29 - 58 (30 bit)
access : read-write


DATA

ADC Output Data
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 adc_data

adc_data : ADC Converted Sample Data Output
bits : 0 - 15 (16 bit)
access : read-only


INTR

ADC Interrupt Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 done_ie ref_ready_ie hi_limit_ie lo_limit_ie overflow_ie done_if ref_ready_if hi_limit_if lo_limit_if overflow_if pending

done_ie : ADC Done Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

ref_ready_ie : ADC Reference Ready Interrupt Enable
bits : 1 - 2 (2 bit)
access : read-write

hi_limit_ie : ADC Hi Limit Monitor Interrupt Enable
bits : 2 - 4 (3 bit)
access : read-write

lo_limit_ie : ADC Lo Limit Monitor Interrupt Enable
bits : 3 - 6 (4 bit)
access : read-write

overflow_ie : ADC Overflow Interrupt Enable
bits : 4 - 8 (5 bit)
access : read-write

done_if : ADC Done Interrupt Flag
bits : 16 - 32 (17 bit)
access : read-write

ref_ready_if : ADC Reference Ready Interrupt Flag
bits : 17 - 34 (18 bit)
access : read-write

hi_limit_if : ADC Hi Limit Monitor Interrupt Flag
bits : 18 - 36 (19 bit)
access : read-write

lo_limit_if : ADC Lo Limit Monitor Interrupt Flag
bits : 19 - 38 (20 bit)
access : read-write

overflow_if : ADC Overflow Interrupt Flag
bits : 20 - 40 (21 bit)
access : read-write

pending : ADC Interrupt Pending Status
bits : 22 - 44 (23 bit)
access : read-only



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