Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Crypto Control Register.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RST : Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle.
bits : 0 - 0 (1 bit)
Enumeration: reset_read ( read )
0 : reset_done
Reset complete.
1 : busy
Reset in progress.
1 : reset
Starts reset operation.
End of enumeration elements list.
INTR : Interrupt Enable. Generates an interrupt when done or error set.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable
1 : en
Enable
End of enumeration elements list.
SRC : Source Select. This bit selects the hash function and CRC generator input source.
bits : 2 - 2 (1 bit)
Enumeration:
0 : inputFIFO
Input FIFO
1 : outputFIFO
Output FIFO
End of enumeration elements list.
BSO : Byte Swap Output. Note. No byte swap will occur if there is not a full word.
bits : 4 - 4 (1 bit)
BSI : Byte Swap Input. Note. No byte swap will occur if there is not a full word.
bits : 5 - 5 (1 bit)
WAIT_EN : Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready.
bits : 6 - 6 (1 bit)
WAIT_POL : Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state.
bits : 7 - 7 (1 bit)
Enumeration:
0 : activeLo
Active Low.
1 : activeHi
Active High.
End of enumeration elements list.
WRSRC : Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled.
bits : 8 - 9 (2 bit)
Enumeration:
0 : none
None.
1 : cipherOutput
Cipher Output.
2 : readFIFO
Read FIFO.
3 : RFU
Reserved. Do not use.
End of enumeration elements list.
RDSRC : Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator.
bits : 10 - 11 (2 bit)
Enumeration:
0 : dmaDisabled
DMA Disable.
1 : dmaOrApb
DMA Or APB.
2 : rng
RNG.
End of enumeration elements list.
FLAG_MODE : Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs.
bits : 14 - 14 (1 bit)
Enumeration:
0 : unres_wr
Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags.
1 : res_wr
Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect.
End of enumeration elements list.
DMADNEMSK : DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA.
bits : 15 - 15 (1 bit)
Enumeration:
0 : not_used
DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.
1 : used
DMA_DONE used in setting CRYPTO_CTRL.DONE bit.
End of enumeration elements list.
DMA_DONE : DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation.
bits : 24 - 24 (1 bit)
Enumeration:
0 : notDone
Not Done.
1 : done
Done.
End of enumeration elements list.
GLS_DONE : Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator.
bits : 25 - 25 (1 bit)
HSH_DONE : Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation.
bits : 26 - 26 (1 bit)
CPH_DONE : Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation.
bits : 27 - 27 (1 bit)
MAA_DONE : MAA Done. MAA operation is complete. This bit must be cleared before starting a new MAA operation. This bit is read only while the MAA is in progress. This bit is negate of MAA_CTRL.STC.
bits : 28 - 28 (1 bit)
ERR : AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : noError
No Error.
1 : error
Error.
End of enumeration elements list.
RDY : Ready. Crypto block ready for more data.
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : busy
Busy.
1 : ready
Ready.
End of enumeration elements list.
DONE : Done. One or more cryptographic calculations complete (logical OR of done flags).
bits : 31 - 31 (1 bit)
access : read-only
Crypto DMA Source Address.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : DMA Source Address.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
address_offset : 0x108 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x124 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Crypto DMA Destination Address.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : DMA Destination Address.
bits : 0 - 31 (32 bit)
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto DMA Byte Count.
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : DMA Byte Address.
bits : 0 - 31 (32 bit)
Message Size. This register holds the lowest 32-bit of message size in bytes.
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGSZ : Message Size. This register holds the lowest 32-bit of message size in bytes.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x18C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
MAA Control Register.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STC : Start Calculation. This bit functions as both the control and the status of the MAA. If the size value in the MAWS register is invalid, the STC bit will be cleared by hardware immediately. Otherwise, the STC bit is automatically cleared following the completion of each calculation or detecting an error. Clearing the STC bit resets the controller to its default state.
bits : 0 - 0 (1 bit)
Enumeration:
0 : nop
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
CLC : Calculation Configuration. These bits select desired calculation.
bits : 1 - 3 (3 bit)
Enumeration:
0 : exp
Exponentiation.
1 : sq
Square operation.
2 : mul
Multiplication.
3 : sqMul
Square followed by a multiplication.
4 : add
Addition.
5 : sub
Subtraction.
End of enumeration elements list.
OCALC : Optimized Calculation Control. For optimized calculation, unnecessary multiply operations after normalizing the exponent are skipped.
bits : 4 - 4 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
MAAER : MAA Error. The MAAER bit defaults to 0 and can only be set by hardware. Once set, it must be cleared by software otherwise no new operation can be initiated. Software writes 1 to this bit has no effect and MAAER will maintain its original state.
bits : 7 - 7 (1 bit)
Enumeration:
0 : noError
No Error.
1 : error
Error.
End of enumeration elements list.
AMS : Multiplier A Memory Select. These bits select the starting position of the parameter 'a' within the logical segment specified by AMA.
bits : 8 - 9 (2 bit)
BMS : Multiplicand B Memory Select. These bits select the starting position of the parameter 'b' within the logical segment specified by BMA.
bits : 10 - 11 (2 bit)
EMS : Exponent Memory Select. These bits select the starting position of the parameter 'e' within the logical segment specified by EMA.
bits : 12 - 13 (2 bit)
MMS : Modulus Memory Select. These bits select the starting position of the parameter 'm' within the logical segment 5.
bits : 14 - 15 (2 bit)
AMA : Multiplier / Operand A Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'a'.
bits : 16 - 19 (4 bit)
BMA : Multiplicand / Operand B Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'b'.
bits : 20 - 23 (4 bit)
RMA : Result Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 'r'.
bits : 24 - 27 (4 bit)
TMA : Temporary Memory Assignment. These bits select the logical cryptographic RAM segment for the parameter 't'.
bits : 28 - 31 (4 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x1F8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)
Message Size. This register holds the lowest 32-bit of message size in bytes.
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGSZ : Message Size. This register holds the lowest 32-bit of message size in bytes.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x268 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x2DC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)
Message Size. This register holds the lowest 32-bit of message size in bytes.
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGSZ : Message Size. This register holds the lowest 32-bit of message size in bytes.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x354 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x3BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x3D0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Message Size. This register holds the lowest 32-bit of message size in bytes.
address_offset : 0x3D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGSZ : Message Size. This register holds the lowest 32-bit of message size in bytes.
bits : 0 - 31 (32 bit)
Cipher Control Register.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENC : Encrypt. Select encryption or decryption of input data.
bits : 0 - 0 (1 bit)
Enumeration:
0 : encrypt
Encrypt.
1 : decrypt
Decrypt.
End of enumeration elements list.
KEY : Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag.
bits : 1 - 1 (1 bit)
Enumeration:
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
SRC : Source of Random key.
bits : 2 - 3 (2 bit)
Enumeration:
0 : cipherKey
User cipher key (0x4000_1060).
2 : regFile
Key from battery-backed register file (0x4000_5000 to 0x4000_501F).
3 : qspiKey_regFile
Key from battery-backed register file (0x4000_5020 to 0x4000_502F).
End of enumeration elements list.
CIPHER : Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation.
bits : 4 - 6 (3 bit)
Enumeration:
0 : dis
Disabled.
1 : aes128
AES 128.
2 : aes192
AES 192.
3 : aes256
AES 256.
4 : des
DES.
5 : tdes
Triple DES.
End of enumeration elements list.
MODE : Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes.
bits : 8 - 10 (3 bit)
Enumeration:
0 : ECB
ECB Mode.
1 : CBC
CBC Mode.
2 : CFB
CFB (AES only).
3 : OFB
OFB (AES only).
4 : CTR
CTR (AES only).
End of enumeration elements list.
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
address_offset : 0x40 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)
CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POLY : CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.
bits : 0 - 31 (32 bit)
CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit.
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x454 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Pseudo Random Value. Output of the Galois Field shift register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled.
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRNG : Pseudo Random Value. Output of the Galois Field Shift Register. This holds the resulting pseudo-random number if entropy is disabled or true random number if entropy is enabled.
bits : 0 - 31 (32 bit)
Hamming ECC Register.
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC : Hamming ECC Value. These bits are the even parity of their corresponding bit groups.
bits : 0 - 15 (16 bit)
PAR : Parity. This is the parity of the entire array.
bits : 16 - 16 (1 bit)
Enumeration:
0 : even
Even.
1 : odd
Odd.
End of enumeration elements list.
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x4F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
address_offset : 0x50 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
address_offset : 0x54 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x590 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
address_offset : 0x5C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x60 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x634 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
address_offset : 0x64 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x6DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x78 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x788 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0x7C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
HASH Control Register.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT : Initialize. Initializes hash registers with standard constants.
bits : 0 - 0 (1 bit)
Enumeration:
0 : nop
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
XOR : XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
HASH : Hash function selection.
bits : 2 - 4 (3 bit)
Enumeration:
0 : dis
Disabled.
1 : sha1
SHA-1.
2 : sha224
SHA 224.
3 : sha256
SHA 256.
4 : sha384
SHA 384.
5 : sha512
SHA 512.
End of enumeration elements list.
LAST : Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash.
bits : 5 - 5 (1 bit)
Enumeration:
0 : noEffect
No Effect.
1 : lastMsgData
Last Message Data.
End of enumeration elements list.
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x80 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x838 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
address_offset : 0x8C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x8EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
address_offset : 0x94 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x94 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x9A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xA0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xA4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xA60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xAC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xB0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xB4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.
address_offset : 0xB8 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Input. Input can be written to this register instead of using DMA.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
This register holds the calculated hash value. This register is affected by the endian swap bits.
address_offset : 0xBC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HASH : This register holds the calculated hash value. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
CRC Control Register.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC : Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
MSB : MSB select. This bit selects the order of calculating CRC on data.
bits : 1 - 1 (1 bit)
Enumeration:
0 : lsbFirst
LSB First.
1 : msbFirst
MSB First.
End of enumeration elements list.
PRNG : Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle.
bits : 2 - 2 (1 bit)
ENT : Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source.
bits : 3 - 3 (1 bit)
HAM : Hamming Code Enable. Enable hamming code calculation.
bits : 4 - 4 (1 bit)
HRST : Hamming Reset. Reset Hamming code ECC generator for next block.
bits : 5 - 5 (1 bit)
access : write-only
Enumeration: ( write )
1 : reset
Starts reset operation.
0 : RFU
Reserved. Do not use.
End of enumeration elements list.
Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.
address_offset : 0xC0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.
bits : 0 - 31 (32 bit)
Message Size. This register holds the lowest 32-bit of message size in bytes.
address_offset : 0xC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGSZ : Message Size. This register holds the lowest 32-bit of message size in bytes.
bits : 0 - 31 (32 bit)
Message Size. This register holds the lowest 32-bit of message size in bytes.
address_offset : 0xC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGSZ : Message Size. This register holds the lowest 32-bit of message size in bytes.
bits : 0 - 31 (32 bit)
Message Size. This register holds the lowest 32-bit of message size in bytes.
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGSZ : Message Size. This register holds the lowest 32-bit of message size in bytes.
bits : 0 - 31 (32 bit)
Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.
address_offset : 0xCC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.
bits : 0 - 31 (32 bit)
Message Size. This register holds the lowest 32-bit of message size in bytes.
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSGSZ : Message Size. This register holds the lowest 32-bit of message size in bytes.
bits : 0 - 31 (32 bit)
MAA Word Size. This register defines the number of bits for a modular operation. This register must be set to a valid value prior to the MAA operation start. Valid values are from 1 to 2048. Invalid values are ignored and will not initiate a MAA operation.
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAWS : MAA Word Size.
bits : 0 - 11 (12 bit)
Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IVEC : Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.
bits : 0 - 31 (32 bit)
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