Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[14]-CH[13]-CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CFG
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-ST
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-SRC_RLD
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-DST_RLD
CH[12]-CH[11]-CH[10]-CH[9]-CH[8]-CH[7]-CH[6]-CH[5]-CH[4]-CH[3]-CH[2]-CH[1]-CH[0]-CNT_RLD
DMA Control Register.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_IEN : Channel 0 Interrupt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CH1_IEN : Channel 1 Interrupt Enable.
bits : 1 - 1 (1 bit)
CH2_IEN : Channel 2 Interrupt Enable.
bits : 2 - 2 (1 bit)
CH3_IEN : Channel 3 Interrupt Enable.
bits : 3 - 3 (1 bit)
CH4_IEN : Channel 4 Interrupt Enable.
bits : 4 - 4 (1 bit)
CH5_IEN : Channel 5 Interrupt Enable.
bits : 5 - 5 (1 bit)
CH6_IEN : Channel 6 Interrupt Enable.
bits : 6 - 6 (1 bit)
CH7_IEN : Channel 7 Interrupt Enable.
bits : 7 - 7 (1 bit)
CH8_IEN : Channel 8 Interrupt Enable.
bits : 8 - 8 (1 bit)
CH9_IEN : Channel 9 Interrupt Enable.
bits : 9 - 9 (1 bit)
CH10_IEN : Channel 10 Interrupt Enable.
bits : 10 - 10 (1 bit)
CH11_IEN : Channel 11 Interrupt Enable.
bits : 11 - 11 (1 bit)
CH12_IEN : Channel 12 Interrupt Enable.
bits : 12 - 12 (1 bit)
CH13_IEN : Channel 13 Interrupt Enable.
bits : 13 - 13 (1 bit)
CH14_IEN : Channel 14 Interrupt Enable.
bits : 14 - 14 (1 bit)
CH15_IEN : Channel 15 Interrupt Enable.
bits : 15 - 15 (1 bit)
DMA Channel Configuration Register.
address_offset : 0x100 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x104 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x106C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x1070 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x1074 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x1078 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x107C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x108 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x1080 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x1084 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x1088 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x10C Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x110 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x114 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x118 Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Configuration Register.
address_offset : 0x11A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x11A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x11AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x11B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x11B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x11B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x11BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x11C Bytes (0x0)
size : 0 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Count Reload Register.
address_offset : 0x11C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x12E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x12E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x12E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x12EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x12F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x12F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x12F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x12FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Interrupt Register.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0_IPEND : Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.
bits : 0 - 0 (1 bit)
Enumeration: ch_ipend_enum
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CH1_IPEND :
bits : 1 - 1 (1 bit)
Enumeration:
End of enumeration elements list.
CH2_IPEND :
bits : 2 - 2 (1 bit)
Enumeration:
End of enumeration elements list.
CH3_IPEND :
bits : 3 - 3 (1 bit)
Enumeration:
End of enumeration elements list.
CH4_IPEND :
bits : 4 - 4 (1 bit)
Enumeration:
End of enumeration elements list.
CH5_IPEND :
bits : 5 - 5 (1 bit)
Enumeration:
End of enumeration elements list.
CH6_IPEND :
bits : 6 - 6 (1 bit)
Enumeration:
End of enumeration elements list.
CH7_IPEND :
bits : 7 - 7 (1 bit)
Enumeration:
End of enumeration elements list.
CH8_IPEND :
bits : 8 - 8 (1 bit)
Enumeration:
End of enumeration elements list.
CH9_IPEND :
bits : 9 - 9 (1 bit)
Enumeration:
End of enumeration elements list.
CH10_IPEND :
bits : 10 - 10 (1 bit)
Enumeration:
End of enumeration elements list.
CH11_IPEND :
bits : 11 - 11 (1 bit)
Enumeration:
End of enumeration elements list.
CH12_IPEND :
bits : 12 - 12 (1 bit)
Enumeration:
End of enumeration elements list.
CH13_IPEND :
bits : 13 - 13 (1 bit)
Enumeration:
End of enumeration elements list.
CH14_IPEND :
bits : 14 - 14 (1 bit)
Enumeration:
End of enumeration elements list.
CH15_IPEND :
bits : 15 - 15 (1 bit)
Enumeration:
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x424 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x52C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x530 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x534 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x628 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x62C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x630 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x634 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x638 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x63C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x640 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x644 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x73C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x740 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x744 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x748 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x74C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x750 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x754 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x758 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x854 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x858 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x85C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x860 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x864 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x868 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x86C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x870 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0x970 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0x974 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0x978 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0x97C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0x980 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0x984 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0x988 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0x98C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0xA90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0xA94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0xA98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0xA9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0xAA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0xAA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0xAA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0xAAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0xBB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0xBB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0xBBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0xBC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0xBC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0xBC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0xBCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0xBD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0xCDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0xCE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0xCE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0xCE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0xCEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0xCF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0xCF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0xCF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0xE08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0xE0C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0xE10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0xE14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0xE18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0xE1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0xE20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0xE24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Configuration Register.
address_offset : 0xF38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
RLDEN : Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRI : DMA Priority.
bits : 2 - 3 (2 bit)
Enumeration:
0 : high
Highest Priority.
1 : medHigh
Medium High Priority.
2 : medLow
Medium Low Priority.
3 : low
Lowest Priority.
End of enumeration elements list.
REQSEL : Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.
bits : 4 - 9 (6 bit)
Enumeration:
0x00 : MEMTOMEM
Memory To Memory
0x01 : SPI0RX
SPI0 RX
0x02 : SPI1RX
SPI1 RX
0x03 : SPI2RX
SPI2 RX
0x04 : UART0RX
UART0 RX
0x05 : UART1RX
UART1 RX
0x07 : I2C0RX
I2C0 RX
0x08 : I2C1RX
I2C1 RX
0x09 : ADC
Analog-to-Digital Converter Channel
0x0E : UART2RX
UART2 RX
0x0F : SPI3RX
SPI3 RX
0x10 : SPI_MSS0RX
SPI MSS0 RX
0x11 : USBRXEP1
USB Endpoint 1 RX
0x12 : USBRXEP2
USB Endpoint 2 RX
0x13 : USBRXEP3
USB Endpoint 3 RX
0x14 : USBRXEP4
USB Endpoint 4 RX
0x15 : USBRXEP5
USB Endpoint 5 RX
0x16 : USBRXEP6
USB Endpoint 6 RX
0x17 : USBRXEP7
USB Endpoint 7 RX
0x18 : USBRXEP8
USB Endpoint 8 RX
0x19 : USBRXEP9
USB Endpoint 9 RX
0x1A : USBRXEP10
USB Endpoint 10 RX
0x1B : USBRXEP11
USB Endpoint 11 RX
0x21 : SPI0TX
SPI0 TX
0x22 : SPI1TX
SPI1 TX
0x23 : SPI2TX
SPI2 TX
0x24 : UART0TX
UART0 TX
0x25 : UART1TX
UART1 TX
0x27 : I2C0TX
I2C0 TX
0x28 : I2C1TX
I2C1 TX
0x2E : UART2TX
UART2 TX
0x2F : SPI3TX
SPI3 TX
0x30 : SPI_MSS0TX
SPI MSS0 TX
0x31 : USBTXEP1
USB Endpoint 1 TX
0x32 : USBTXEP2
USB Endpoint 2 TX
0x33 : USBTXEP3
USB Endpoint 3 TX
0x34 : USBTXEP4
USB Endpoint 4 TX
0x35 : USBTXEP5
USB Endpoint 5 TX
0x36 : USBTXEP6
USB Endpoint 6 TX
0x37 : USBTXEP7
USB Endpoint 7 TX
0x38 : USBTXEP8
USB Endpoint 8 TX
0x39 : USBTXEP9
USB Endpoint 9 TX
0x3A : USBTXEP10
USB Endpoint 10 TX
0x3B : USBTXEP11
USB Endpoint 11 TX
End of enumeration elements list.
REQWAIT : Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
TOSEL : Time-Out Select. Selects the number of prescale clocks seen by the channel timer before a time-out conditions is generated for this channel. Important note: since the prescaler runs independent of the individual channel timers, the actual number of Pre-Scale clock edges seen has a margin of error equal to a single Pre-Scale clock.
bits : 11 - 13 (3 bit)
Enumeration:
0 : to4
Timeout of 3 to 4 prescale clocks.
1 : to8
Timeout of 7 to 8 prescale clocks.
2 : to16
Timeout of 15 to 16 prescale clocks.
3 : to32
Timeout of 31 to 32 prescale clocks.
4 : to64
Timeout of 63 to 64 prescale clocks.
5 : to128
Timeout of 127 to 128 prescale clocks.
6 : to256
Timeout of 255 to 256 prescale clocks.
7 : to512
Timeout of 511 to 512 prescale clocks.
End of enumeration elements list.
PSSEL : Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.
bits : 14 - 15 (2 bit)
Enumeration:
0 : dis
Disable timer.
1 : div256
hclk / 256.
2 : div64k
hclk / 64k.
3 : div16M
hclk / 16M.
End of enumeration elements list.
SRCWD : Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.
bits : 16 - 17 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
SRCINC : Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DSTWD : Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).
bits : 20 - 21 (2 bit)
Enumeration:
0 : byte
Byte.
1 : halfWord
Halfword.
2 : word
Word.
End of enumeration elements list.
DSTINC : Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BRST : Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.
bits : 24 - 28 (5 bit)
CHDIEN : Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.
bits : 30 - 30 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
CTZIEN : Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
DMA Channel Status Register.
address_offset : 0xF3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH_ST : Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
IPEND : Channel Interrupt.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
CTZ_ST : Count-to-Zero (CTZ) Status
bits : 2 - 2 (1 bit)
Enumeration: ctz_st_enum_wr ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
RLD_ST : Reload Status.
bits : 3 - 3 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
BUS_ERR : Bus Error. Indicates that an AHB abort was received and the channel has been disabled.
bits : 4 - 4 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
TO_ST : Time-Out Status.
bits : 6 - 6 (1 bit)
Enumeration: ( write )
1 : Clear
Clears the interrupt flag
End of enumeration elements list.
Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.
address_offset : 0xF40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.
address_offset : 0xF44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR :
bits : 0 - 31 (32 bit)
DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.
address_offset : 0xF48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : DMA Counter.
bits : 0 - 23 (24 bit)
Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.
address_offset : 0xF4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_RLD : Source Address Reload Value.
bits : 0 - 30 (31 bit)
Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.
address_offset : 0xF50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DST_RLD : Destination Address Reload Value.
bits : 0 - 30 (31 bit)
DMA Channel Count Reload Register.
address_offset : 0xF54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT_RLD : Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.
bits : 0 - 23 (24 bit)
RLDEN : Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
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