Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Flash Write Address.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address for next operation.
bits : 0 - 31 (32 bit)
Flash Write Address.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Address for next operation.
bits : 0 - 31 (32 bit)
Flash Write Data.
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data next operation.
bits : 0 - 31 (32 bit)
Flash Interrupt Register.
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.
bits : 0 - 0 (1 bit)
Enumeration:
0 : inactive
No interrupt is pending
1 : pending
An interrupt is pending
End of enumeration elements list.
AF : Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.
bits : 1 - 1 (1 bit)
Enumeration:
0 : noError
No Failure.
1 : error
Failure occurs.
End of enumeration elements list.
DONEIE : Flash Done Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : disable
Disable.
1 : enable
Enable.
End of enumeration elements list.
AFIE :
bits : 9 - 9 (1 bit)
Flash Interrupt Register.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DONE : Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.
bits : 0 - 0 (1 bit)
Enumeration:
0 : inactive
No interrupt is pending
1 : pending
An interrupt is pending
End of enumeration elements list.
AF : Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.
bits : 1 - 1 (1 bit)
Enumeration:
0 : noError
No Failure.
1 : error
Failure occurs.
End of enumeration elements list.
DONEIE : Flash Done Interrupt Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : disable
Disable.
1 : enable
Enable.
End of enumeration elements list.
AFIE :
bits : 9 - 9 (1 bit)
Flash Write Data.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data next operation.
bits : 0 - 31 (32 bit)
Flash Write Data.
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data next operation.
bits : 0 - 31 (32 bit)
Flash Write Data.
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data next operation.
bits : 0 - 31 (32 bit)
Flash Write Data.
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data next operation.
bits : 0 - 31 (32 bit)
Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.
bits : 0 - 7 (8 bit)
Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.
bits : 0 - 7 (8 bit)
Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.
address_offset : 0x40 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ACNTL : Access control.
bits : 0 - 31 (32 bit)
Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3 pflc-acntl = 0xa1e34f20 pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ACNTL : Access control.
bits : 0 - 31 (32 bit)
Flash Write Data.
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data next operation.
bits : 0 - 31 (32 bit)
Flash Control Register.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR : Write. This bit is automatically cleared after the operation.
bits : 0 - 0 (1 bit)
Enumeration:
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
ME : Mass Erase. This bit is automatically cleared after the operation.
bits : 1 - 1 (1 bit)
PGE : Page Erase. This bit is automatically cleared after the operation.
bits : 2 - 2 (1 bit)
WDTH : Data Width. This bits selects write data width.
bits : 4 - 4 (1 bit)
Enumeration:
0 : size128
128-bit.
1 : size32
32-bit.
End of enumeration elements list.
ERASE_CODE : Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.
bits : 8 - 15 (8 bit)
Enumeration:
0 : nop
No operation.
0x55 : erasePage
Enable Page Erase.
0xAA : eraseAll
Enable Mass Erase. The debug port must be enabled.
End of enumeration elements list.
PEND : Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : idle
Idle.
1 : busy
Busy.
End of enumeration elements list.
LVE : Low Voltage Read Enable
bits : 25 - 25 (1 bit)
access : read-only
Enumeration: lve_read ( read )
0 : dis
Disabled
1 : en
Enabled
End of enumeration elements list.
BRST : Burst Mode Enable.
bits : 27 - 27 (1 bit)
Enumeration:
0 : disable
Disable
1 : enable
Enable
End of enumeration elements list.
UNLOCK : Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.
bits : 28 - 31 (4 bit)
Enumeration:
2 : unlocked
Flash Unlocked
End of enumeration elements list.
Flash Control Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WR : Write. This bit is automatically cleared after the operation.
bits : 0 - 0 (1 bit)
Enumeration:
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
ME : Mass Erase. This bit is automatically cleared after the operation.
bits : 1 - 1 (1 bit)
PGE : Page Erase. This bit is automatically cleared after the operation.
bits : 2 - 2 (1 bit)
WDTH : Data Width. This bits selects write data width.
bits : 4 - 4 (1 bit)
Enumeration:
0 : size128
128-bit.
1 : size32
32-bit.
End of enumeration elements list.
ERASE_CODE : Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.
bits : 8 - 15 (8 bit)
Enumeration:
0 : nop
No operation.
0x55 : erasePage
Enable Page Erase.
0xAA : eraseAll
Enable Mass Erase. The debug port must be enabled.
End of enumeration elements list.
PEND : Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : idle
Idle.
1 : busy
Busy.
End of enumeration elements list.
LVE : Low Voltage Read Enable
bits : 25 - 25 (1 bit)
access : read-only
Enumeration: lve_read ( read )
0 : dis
Disabled
1 : en
Enabled
End of enumeration elements list.
BRST : Burst Mode Enable.
bits : 27 - 27 (1 bit)
Enumeration:
0 : disable
Disable
1 : enable
Enable
End of enumeration elements list.
UNLOCK : Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.
bits : 28 - 31 (4 bit)
Enumeration:
2 : unlocked
Flash Unlocked
3 : locked
Flash Locked
End of enumeration elements list.
Flash Write Data.
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data next operation.
bits : 0 - 31 (32 bit)
Flash Write Data.
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data next operation.
bits : 0 - 31 (32 bit)
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