SCON

PLL0CN

PLL1CN

PCKDIV

PERCKCN0

MEMCKCN

MEMZCN

SCCK

MPRI0

MPRI1

RSTR0

SYSST

RSTR1

PERCKCN1

EVTEN

REVISION

SYSSIE

CLKCN

PM

BSTAPEN : Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

SBUSARB : System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.
bits : 1 - 2 (2 bit)

Enumeration:

End of enumeration elements list.

FLASH_PAGE_FLIP : Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

CCACHE_FLUSH : Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4.
bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

DCACHE_FLUSH : Data Cache Flush. The system cache(s) will be flushed when this bit is set.
bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

DCACHE_DIS : Data Cache Disable. The system cache(s) will be completely disabled when this bit is set.
bits : 9 - 9 (1 bit)

Enumeration:

End of enumeration elements list.

CCHK : Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.
bits : 13 - 13 (1 bit)

Enumeration:

End of enumeration elements list.

CHKRES : ROM Checksum Result. This bit is only valid when CHKRD=1.
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

OVR : Operating Voltage Range. Setting these bits according to the VCore voltage allows the on-chip Random-Access memories to operate in their optimal timing range.
bits : 16 - 17 (2 bit)

Enumeration:

End of enumeration elements list.

RFU : Reserved for Future Use
bits : 0 - 31 (32 bit)

RFU : Reserved for Future Use
bits : 0 - 31 (32 bit)

PCF : These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware.
bits : 0 - 2 (3 bit)

Enumeration:

End of enumeration elements list.

PCFWEN : PCF Write Enable. This bit allows the PCF Register bits to be updated by Software.
bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

SDHCFRQ : SDHC Clock Frequency. This bits defines the clock frequency of SDHC.
bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

ADCFRQ : ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/(ADCFRQ).
bits : 10 - 13 (4 bit)

AONCD : Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider.
bits : 14 - 15 (2 bit)

Enumeration:

End of enumeration elements list.

GPIO0D : GPIO0 Disable.
bits : 0 - 0 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

GPIO1D : GPIO1 Disable.
bits : 1 - 1 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

GPIO2D : GPIO2 Disable.
bits : 2 - 2 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

USBD : USB Disable.
bits : 3 - 3 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

CLCDD : CLCD Disable.
bits : 4 - 4 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

DMAD : DMA Disable.
bits : 5 - 5 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

SPI0D : SPI 0 Disable.
bits : 6 - 6 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

SPI1D : SPI 1 Disable.
bits : 7 - 7 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

SPI2D : SPI 2 Disable.
bits : 8 - 8 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

UART0D : UART 0 Disable.
bits : 9 - 9 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

UART1D : UART 1 Disable.
bits : 10 - 10 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

I2C0D : I2C 0 Disable.
bits : 13 - 13 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

CRYPTOD : Crypto Disable.
bits : 14 - 14 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

T0D : Timer 0 Disable.
bits : 15 - 15 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

T1D : Timer 1 Disable.
bits : 16 - 16 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

T2D : Timer 2 Disable.
bits : 17 - 17 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

T3D : Timer 3 Disable.
bits : 18 - 18 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

T4D : Timer 4 Disable.
bits : 19 - 19 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

T5D : Timer 5 Disable.
bits : 20 - 20 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

ADCD : ADC Disable.
bits : 23 - 23 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

RSV_0X19 : Reserved for Future Use
bits : 25 - 25 (1 bit)

I2C1D : I2C 1 Disable.
bits : 28 - 28 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

PTD : PT Clock Disable.
bits : 29 - 29 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

SPIXIPD : SPI XiP Disable.
bits : 30 - 30 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

SPIMD : SPI XiP Master Controller Disable.
bits : 31 - 31 (1 bit)

Enumeration: GPIODisable

End of enumeration elements list.

FWS : Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
bits : 0 - 2 (3 bit)

SYSRAM0LS : System RAM 0 Light Sleep Mode.
bits : 16 - 16 (1 bit)

Enumeration:

End of enumeration elements list.

SYSRAM1LS : System RAM 1 Light Sleep Mode.
bits : 17 - 17 (1 bit)

Enumeration:

End of enumeration elements list.

SYSRAM2LS : System RAM 2 Light Sleep Mode.
bits : 18 - 18 (1 bit)

Enumeration:

End of enumeration elements list.

SYSRAM3LS : System RAM 3 Light Sleep Mode.
bits : 19 - 19 (1 bit)

Enumeration:

End of enumeration elements list.

SYSRAM4LS : System RAM 4 Light Sleep Mode.
bits : 20 - 20 (1 bit)

Enumeration:

End of enumeration elements list.

SYSRAM5LS : System RAM 5 Light Sleep Mode.
bits : 21 - 21 (1 bit)

Enumeration:

End of enumeration elements list.

SYSRAM6LS : System RAM 6 Light Sleep Mode.
bits : 22 - 22 (1 bit)

Enumeration:

End of enumeration elements list.

ICACHELS : ICache RAM Light Sleep Mode.
bits : 24 - 24 (1 bit)

Enumeration:

End of enumeration elements list.

ICACHEXIPLS : ICACHE-XIP RAM Light Sleep Mode.
bits : 25 - 25 (1 bit)

Enumeration:

End of enumeration elements list.

SCACHELS : SysCache RAM Light Sleep Mode.
bits : 26 - 26 (1 bit)

Enumeration:

End of enumeration elements list.

CRYPTOLS : CRYPTO RAM Light Sleep Mode.
bits : 27 - 27 (1 bit)

Enumeration:

End of enumeration elements list.

USBLS : USB FIFO Light Sleep Mode.
bits : 28 - 28 (1 bit)

Enumeration:

End of enumeration elements list.

ROMLS : ROM Light Sleep Mode.
bits : 29 - 29 (1 bit)

Enumeration:

End of enumeration elements list.

SRAM0Z : System RAM Block 0.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

SRAM1Z : System RAM Block 1.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

SRAM2Z : System RAM Block 2.
bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

SRAM3Z : System RAM Block 3.
bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

SRAM4Z : System RAM Block 4.
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

SRAM5Z : System RAM Block 5.
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

SRAM6Z : System RAM Block 6.
bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

ICACHEZ : Instruction Cache.
bits : 8 - 8 (1 bit)

Enumeration:

End of enumeration elements list.

ICACHEXIPZ : Instruction Cache XIP Data and Tag Ram zeroizatoin.
bits : 9 - 9 (1 bit)

Enumeration:

End of enumeration elements list.

SCACHEDATAZ : System Cache Data Ram Zeroization.
bits : 10 - 10 (1 bit)

Enumeration:

End of enumeration elements list.

SCACHETAGZ : System Cache Tag Zeroization.
bits : 11 - 11 (1 bit)

Enumeration:

End of enumeration elements list.

CRYPTOZ : Crypto (MAA) Memory.
bits : 12 - 12 (1 bit)

Enumeration:

End of enumeration elements list.

USBFIFOZ : USB FIFO Zeroizatoin.
bits : 13 - 13 (1 bit)

Enumeration:

End of enumeration elements list.

DMA : DMA Reset.
bits : 0 - 0 (1 bit)

Enumeration: dma_read ( read )

End of enumeration elements list.

WDT : Watchdog Timer Reset.
bits : 1 - 1 (1 bit)

Enumeration: wdt_read ( read )

End of enumeration elements list.

GPIO0 : GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.
bits : 2 - 2 (1 bit)

Enumeration: gpio0_read ( read )

End of enumeration elements list.

GPIO1 : GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.
bits : 3 - 3 (1 bit)

Enumeration: gpio1_read ( read )

End of enumeration elements list.

GPIO2 : GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states.
bits : 4 - 4 (1 bit)

Enumeration: gpio2_read ( read )

End of enumeration elements list.

TIMER0 : Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.
bits : 5 - 5 (1 bit)

Enumeration: timer0_read ( read )

End of enumeration elements list.

TIMER1 : Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.
bits : 6 - 6 (1 bit)

Enumeration: timer1_read ( read )

End of enumeration elements list.

TIMER2 : Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.
bits : 7 - 7 (1 bit)

Enumeration: timer2_read ( read )

End of enumeration elements list.

TIMER3 : Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.
bits : 8 - 8 (1 bit)

Enumeration: timer3_read ( read )

End of enumeration elements list.

TIMER4 : Timer3 Reset. Setting this bit to 1 resets Timer 4 blocks.
bits : 9 - 9 (1 bit)

Enumeration: timer4_read ( read )

End of enumeration elements list.

TIMER5 : Timer3 Reset. Setting this bit to 1 resets Timer 5 blocks.
bits : 10 - 10 (1 bit)

Enumeration: timer5_read ( read )

End of enumeration elements list.

UART0 : UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.
bits : 11 - 11 (1 bit)

Enumeration: uart0_read ( read )

End of enumeration elements list.

UART1 : UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.
bits : 12 - 12 (1 bit)

Enumeration: uart1_read ( read )

End of enumeration elements list.

SPI0 : SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.
bits : 13 - 13 (1 bit)

Enumeration: spi0_read ( read )

End of enumeration elements list.

SPI1 : SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.
bits : 14 - 14 (1 bit)

Enumeration: xpi1_read ( read )

End of enumeration elements list.

SPI2 : SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks.
bits : 15 - 15 (1 bit)

Enumeration: spi2_read ( read )

End of enumeration elements list.

I2C0 : I2C0 Reset.
bits : 16 - 16 (1 bit)

Enumeration: i2c0_read ( read )

End of enumeration elements list.

RTC : Real Time Clock Reset.
bits : 17 - 17 (1 bit)

Enumeration: rtc_read ( read )

End of enumeration elements list.

CRYPTO : Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.
bits : 18 - 18 (1 bit)

Enumeration: crypto_read ( read )

End of enumeration elements list.

HBC : Hyper Bus Controller Reset. Setting this bit to 1 resets the HBC clock.
bits : 21 - 21 (1 bit)

Enumeration: hbc_read ( read )

End of enumeration elements list.

CLCD : CLCD Reset. Setting this bit to 1 resets the CLCD clock.
bits : 22 - 22 (1 bit)

Enumeration: clcd_read ( read )

End of enumeration elements list.

USB : USB Reset. Setting this bit resets both USB blocks.
bits : 23 - 23 (1 bit)

Enumeration: usb_read ( read )

End of enumeration elements list.

TRNG : TRNG Reset.
bits : 24 - 24 (1 bit)

Enumeration: trng_read ( read )

End of enumeration elements list.

RSV_0x19 : Reserved for Future Use
bits : 25 - 25 (1 bit)

ADC : Analog to Digital Reset.
bits : 26 - 26 (1 bit)

Enumeration: adc_read ( read )

End of enumeration elements list.

UART2 : UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.
bits : 28 - 28 (1 bit)

Enumeration: uart2_read ( read )

End of enumeration elements list.

SRST : Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.
bits : 29 - 29 (1 bit)

Enumeration: srst_read ( read )

End of enumeration elements list.

PRST : Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.
bits : 30 - 30 (1 bit)

Enumeration: prst_read ( read )

End of enumeration elements list.

SYSTEM : System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.
bits : 31 - 31 (1 bit)

Enumeration: system_read ( read )

End of enumeration elements list.

ICECLOCK : ARM ICE Lock Status.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

CODEINTERR : Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

SCMEMF : System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

I2C1 : I2C1 Reset.
bits : 0 - 0 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

PT : PT Reset.
bits : 1 - 1 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

RSV_0X02 : Reserved for Future Use
bits : 2 - 2 (1 bit)

SPIXIP : SPI XiP Master Reset.
bits : 3 - 3 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

XSPIM : GSPI XiP Master Controller Reset.
bits : 4 - 4 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

GPIO3 : GPIO3 Reset.
bits : 5 - 5 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

SDHC : SDHC/SDIO Reset.
bits : 6 - 6 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

OWIRE : OWIRE Reset.
bits : 7 - 7 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

WDT1 : WDT1 Reset.
bits : 8 - 8 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

SPI3 : SPI3 Reset.
bits : 9 - 9 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

I2S : I2S Reset.
bits : 10 - 10 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

SPIMM0 : SPIMM0 Reset.
bits : 11 - 11 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

SPIMM1 : SPIMM1 Reset.
bits : 12 - 12 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

SPIMM2 : SPIMM2 Reset.
bits : 13 - 13 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

SPIMS0 : SPIMS0 Reset.
bits : 14 - 14 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

SPIXMEM : SPIXMEM Reset.
bits : 15 - 15 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

SMPHR : SMPHR Reset.
bits : 16 - 16 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

UART2D : BTLE Disable.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

TRNGD : TRNG Disable.
bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

FLCD : Secure Flash Controller Disable.
bits : 3 - 3 (1 bit)

Enumeration:

End of enumeration elements list.

HBCD : Hyper Bus Controller Clock Disable.
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

RSV_0X05 : Reserved for Future Use
bits : 5 - 5 (1 bit)

GPIO3D : GPIO3 Clock Disable.
bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

SCACHED : System Cache Clock Disable.
bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

SDMAD : SDMA Clock Disable.
bits : 8 - 8 (1 bit)

Enumeration:

End of enumeration elements list.

SMPHRD : Semaphore Clock Disable.
bits : 9 - 9 (1 bit)

Enumeration:

End of enumeration elements list.

SDHCD : SDHC/SDIO Clock Disable.
bits : 10 - 10 (1 bit)

Enumeration:

End of enumeration elements list.

ICACHED : ICache Clock Disable.
bits : 11 - 11 (1 bit)

Enumeration:

End of enumeration elements list.

ICACHEXIPD : ICache XIP Clock Disable.
bits : 12 - 12 (1 bit)

Enumeration:

End of enumeration elements list.

OWIRED : One-Wire Clock Disable.
bits : 13 - 13 (1 bit)

Enumeration:

End of enumeration elements list.

SPI3D : SPI3 Clock Disable.
bits : 14 - 14 (1 bit)

Enumeration:

End of enumeration elements list.

I2SD : I2S(SPI_MSS) Clock Disable
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

SPIMM0 : SPI Medical Master 0 Clock Disable.
bits : 16 - 16 (1 bit)

Enumeration:

End of enumeration elements list.

SPIMM1 : SPI Medical Master 1 Clock Disable.
bits : 17 - 17 (1 bit)

Enumeration:

End of enumeration elements list.

SPIMM2 : SPI Medical Master 2 Clock Disable.
bits : 18 - 18 (1 bit)

Enumeration:

End of enumeration elements list.

SPIMS0 : SPI Medical Slave 0 Clock Disable.
bits : 19 - 19 (1 bit)

Enumeration:

End of enumeration elements list.

SPIXIPDD : SPI-XIP Data Clock Disable
bits : 20 - 20 (1 bit)

Enumeration:

End of enumeration elements list.

DMAEVENT : Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.
bits : 0 - 0 (1 bit)

RXEVENT : Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode.
bits : 1 - 1 (1 bit)

TXEVENT : Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].
bits : 2 - 2 (1 bit)

REVISION : Manufacturer Chip Revision.
bits : 0 - 15 (16 bit)

ICEULIE : ARM ICE Unlock Interrupt Enable.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

CIEIE : Code Integrity Error Interrupt Enable.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

SCMFIE : System Cache Memory Fault Interrupt Enable.
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

PSC : Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.
bits : 6 - 8 (3 bit)

Enumeration:

End of enumeration elements list.

CLKSEL : Clock Source Select. This 3 bit field selects the source for the system clock.
bits : 9 - 11 (3 bit)

Enumeration:

End of enumeration elements list.

CKRDY : Clock Ready. This read only bit reflects whether the currently selected system clock source is running.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CCD : Cryptographic clock divider
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

X32K_EN : 32kHz Crystal Oscillator Enable.
bits : 17 - 17 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC_EN : 60MHz High Frequency Internal Reference Clock Enable.
bits : 18 - 18 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC96M_EN : 96MHz High Frequency Internal Reference Clock Enable.
bits : 19 - 19 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC8M_EN : 8MHz High Frequency Internal Reference Clock Enable.
bits : 20 - 20 (1 bit)

Enumeration:

End of enumeration elements list.

X32K_RDY : 32kHz Crystal Oscillator Ready
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRC_RDY : 60MHz HIRC Ready.
bits : 26 - 26 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC96M_RDY : 96MHz HIRC Ready.
bits : 27 - 27 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC8M_RDY : 8MHz HIRC Ready.
bits : 28 - 28 (1 bit)

Enumeration:

End of enumeration elements list.

LIRC8K_RDY : 8kHz Low Frequency Reference Clock Ready.
bits : 29 - 29 (1 bit)

Enumeration:

End of enumeration elements list.

MODE : Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.
bits : 0 - 2 (3 bit)

Enumeration:

End of enumeration elements list.

GPIOWKEN : GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

RTCWKEN : RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

USBWKEN : USB Wake Up Enable. This bit enables USB activity as wakeup source.
bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

HIRCPD : HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode.
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC96MPD : 96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode.
bits : 16 - 16 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC8MPD : 8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode.
bits : 17 - 17 (1 bit)

Enumeration:

End of enumeration elements list.