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HPB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

STATUS

MBR0

MBR1

MBR[0]

MCR0

MCR1

MTR0

MBR[1]

MTR1

INTEN

MCR[0]

MTR[0]

MCR[1]

INTFL

MTR[1]


STATUS

Controller Status Register.
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RACT RDECERR RRSTOERR RDSSTALL WACT WDECERR WRSTOERR

RACT : Read Transaction Active.
bits : 0 - 0 (1 bit)
access : read-only

RDECERR : Decode Error in Read Transaction.
bits : 8 - 16 (9 bit)
access : read-only

RRSTOERR : RSTO Error in Read Transaction.
bits : 10 - 20 (11 bit)
access : read-only

RDSSTALL : RDS Stall Error in Read Transaction.
bits : 11 - 22 (12 bit)
access : read-only

WACT : Write Transaction Active.
bits : 16 - 32 (17 bit)
access : read-only

WDECERR : Decode Error in Write Transaction.
bits : 24 - 48 (25 bit)
access : read-only

WRSTOERR : RSTO Error in Write Transaction.
bits : 26 - 52 (27 bit)
access : read-only


MBR0

Memory Base Address Registers.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBR0 MBR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Base address for memory space 0.
bits : 24 - 55 (32 bit)
access : read-write


MBR1

Memory Base Address Registers.
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBR1 MBR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Base address for memory space 0.
bits : 24 - 55 (32 bit)
access : read-write


MBR[0]

Memory Base Address Registers.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBR[0] MBR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Base address for memory space 0.
bits : 24 - 55 (32 bit)
access : read-write


MCR0

Memory Configuration Registers.
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR0 MCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVTYPE CRT FRL HSE MAXLEN MAXEN

DEVTYPE : Device Type.
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

0 : HYPER_FLASH

Hyper flash device.

1 : XCCELA_PSRAM

Hyper PSRAM device.

2 : HYPER_RAM

Hyper RAM device.

End of enumeration elements list.

CRT : Configuration Register Target.
bits : 5 - 10 (6 bit)
access : read-write

FRL : Fixed Read latency enable.
bits : 6 - 12 (7 bit)
access : read-write

HSE : Halt Sleep Exit.
bits : 7 - 14 (8 bit)
access : read-write

MAXLEN : Maximum Length.
bits : 18 - 44 (27 bit)
access : read-write

MAXEN : Maximum length Enable.
bits : 31 - 62 (32 bit)
access : read-write


MCR1

Memory Configuration Registers.
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR1 MCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVTYPE CRT FRL HSE MAXLEN MAXEN

DEVTYPE : Device Type.
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

0 : HYPER_FLASH

Hyper flash device.

1 : XCCELA_PSRAM

Hyper PSRAM device.

2 : HYPER_RAM

Hyper RAM device.

End of enumeration elements list.

CRT : Configuration Register Target.
bits : 5 - 10 (6 bit)
access : read-write

FRL : Fixed Read latency enable.
bits : 6 - 12 (7 bit)
access : read-write

HSE : Halt Sleep Exit.
bits : 7 - 14 (8 bit)
access : read-write

MAXLEN : Maximum Length.
bits : 18 - 44 (27 bit)
access : read-write

MAXEN : Maximum length Enable.
bits : 31 - 62 (32 bit)
access : read-write


MTR0

Memory Timing Registers.
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTR0 MTR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTCY WCSH RCSH WCSS RCSS WCSHI RCSHI

LTCY : Latency Cycle for HyperRAM mode.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 5CLOCK

5 clock latency.

1 : 6CLOCK

6 clock latency.

0xE : 3CLOCK

3 clock latency.

0xF : 4CLOCK

4 clock latency.

End of enumeration elements list.

WCSH : Write Chip Select Hold After CK falling Edge.
bits : 8 - 19 (12 bit)
access : read-write

RCSH : Read Chip Select Hold After CK falling Edge.
bits : 12 - 27 (16 bit)
access : read-write

WCSS : Write Chip Select Setup To Next CK Rising Edge.
bits : 16 - 35 (20 bit)
access : read-write

RCSS : Read Chip Select Setup To Next CK Rising Edge.
bits : 20 - 43 (24 bit)
access : read-write

WCSHI : Write Chip Select High Between Operations.
bits : 24 - 51 (28 bit)
access : read-write

RCSHI : Read Chip Select High Between Operations.
bits : 28 - 59 (32 bit)
access : read-write


MBR[1]

Memory Base Address Registers.
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBR[1] MBR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Base address for memory space 0.
bits : 24 - 55 (32 bit)
access : read-write


MTR1

Memory Timing Registers.
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTR1 MTR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTCY WCSH RCSH WCSS RCSS WCSHI RCSHI

LTCY : Latency Cycle for HyperRAM mode.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 5CLOCK

5 clock latency.

1 : 6CLOCK

6 clock latency.

0xE : 3CLOCK

3 clock latency.

0xF : 4CLOCK

4 clock latency.

End of enumeration elements list.

WCSH : Write Chip Select Hold After CK falling Edge.
bits : 8 - 19 (12 bit)
access : read-write

RCSH : Read Chip Select Hold After CK falling Edge.
bits : 12 - 27 (16 bit)
access : read-write

WCSS : Write Chip Select Setup To Next CK Rising Edge.
bits : 16 - 35 (20 bit)
access : read-write

RCSS : Read Chip Select Setup To Next CK Rising Edge.
bits : 20 - 43 (24 bit)
access : read-write

WCSHI : Write Chip Select High Between Operations.
bits : 24 - 51 (28 bit)
access : read-write

RCSHI : Read Chip Select High Between Operations.
bits : 28 - 59 (32 bit)
access : read-write


INTEN

Interrupt Enable Control Register.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRINTE

ERRINTE : Error Interrupt Enable.
bits : 1 - 2 (2 bit)
access : read-write


MCR[0]

Memory Configuration Registers.
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR[0] MCR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVTYPE CRT FRL HSE MAXLEN MAXEN

DEVTYPE : Device Type.
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

0 : HYPER_FLASH

Hyper flash device.

1 : XCCELA_PSRAM

Hyper PSRAM device.

2 : HYPER_RAM

Hyper RAM device.

End of enumeration elements list.

CRT : Configuration Register Target.
bits : 5 - 10 (6 bit)
access : read-write

FRL : Fixed Read latency enable.
bits : 6 - 12 (7 bit)
access : read-write

HSE : Halt Sleep Exit.
bits : 7 - 14 (8 bit)
access : read-write

MAXLEN : Maximum Length.
bits : 18 - 44 (27 bit)
access : read-write

MAXEN : Maximum length Enable.
bits : 31 - 62 (32 bit)
access : read-write


MTR[0]

Memory Timing Registers.
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTR[0] MTR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTCY WCSH RCSH WCSS RCSS WCSHI RCSHI

LTCY : Latency Cycle for HyperRAM mode.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 5CLOCK

5 clock latency.

1 : 6CLOCK

6 clock latency.

0xE : 3CLOCK

3 clock latency.

0xF : 4CLOCK

4 clock latency.

End of enumeration elements list.

WCSH : Write Chip Select Hold After CK falling Edge.
bits : 8 - 19 (12 bit)
access : read-write

RCSH : Read Chip Select Hold After CK falling Edge.
bits : 12 - 27 (16 bit)
access : read-write

WCSS : Write Chip Select Setup To Next CK Rising Edge.
bits : 16 - 35 (20 bit)
access : read-write

RCSS : Read Chip Select Setup To Next CK Rising Edge.
bits : 20 - 43 (24 bit)
access : read-write

WCSHI : Write Chip Select High Between Operations.
bits : 24 - 51 (28 bit)
access : read-write

RCSHI : Read Chip Select High Between Operations.
bits : 28 - 59 (32 bit)
access : read-write


MCR[1]

Memory Configuration Registers.
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR[1] MCR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEVTYPE CRT FRL HSE MAXLEN MAXEN

DEVTYPE : Device Type.
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

0 : HYPER_FLASH

Hyper flash device.

1 : XCCELA_PSRAM

Hyper PSRAM device.

2 : HYPER_RAM

Hyper RAM device.

End of enumeration elements list.

CRT : Configuration Register Target.
bits : 5 - 10 (6 bit)
access : read-write

FRL : Fixed Read latency enable.
bits : 6 - 12 (7 bit)
access : read-write

HSE : Halt Sleep Exit.
bits : 7 - 14 (8 bit)
access : read-write

MAXLEN : Maximum Length.
bits : 18 - 44 (27 bit)
access : read-write

MAXEN : Maximum length Enable.
bits : 31 - 62 (32 bit)
access : read-write


INTFL

Interrupt Status Register.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTFL INTFL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRINTE

ERRINTE : Error Interrupt Status.
bits : 1 - 2 (2 bit)
access : read-only


MTR[1]

Memory Timing Registers.
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTR[1] MTR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTCY WCSH RCSH WCSS RCSS WCSHI RCSHI

LTCY : Latency Cycle for HyperRAM mode.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0 : 5CLOCK

5 clock latency.

1 : 6CLOCK

6 clock latency.

0xE : 3CLOCK

3 clock latency.

0xF : 4CLOCK

4 clock latency.

End of enumeration elements list.

WCSH : Write Chip Select Hold After CK falling Edge.
bits : 8 - 19 (12 bit)
access : read-write

RCSH : Read Chip Select Hold After CK falling Edge.
bits : 12 - 27 (16 bit)
access : read-write

WCSS : Write Chip Select Setup To Next CK Rising Edge.
bits : 16 - 35 (20 bit)
access : read-write

RCSS : Read Chip Select Setup To Next CK Rising Edge.
bits : 20 - 43 (24 bit)
access : read-write

WCSHI : Write Chip Select High Between Operations.
bits : 24 - 51 (28 bit)
access : read-write

RCSHI : Read Chip Select High Between Operations.
bits : 28 - 59 (32 bit)
access : read-write



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