Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
RTC Second Counter. This register contains the 32-bit second counter.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC Control Register.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTCE : Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
ADE : Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
ASE : Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 2 - 2 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BUSY : RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : idle
Idle.
1 : busy
Busy.
End of enumeration elements list.
RDY : RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.
bits : 4 - 4 (1 bit)
Enumeration:
0 : busy
Register has not updated.
1 : ready
Ready.
End of enumeration elements list.
RDYE : RTC Ready Interrupt Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
ALDF : Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : inactive
Not active
1 : Pending
Active
End of enumeration elements list.
ALSF : Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : inactive
Not active
1 : Pending
Active
End of enumeration elements list.
SQE : Square Wave Output Enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : inactive
Not active
1 : Pending
Active
End of enumeration elements list.
FT : Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.
bits : 9 - 10 (2 bit)
Enumeration:
0 : freq1Hz
1 Hz (Compensated).
1 : freq512Hz
512 Hz (Compensated).
2 : freq4KHz
4 KHz.
3 : clkDiv8
RTC Input Clock / 8.
End of enumeration elements list.
X32KMD : 32KHz Oscillator Mode.
bits : 11 - 12 (2 bit)
Enumeration:
0 : noiseImmuneMode
Always operate in Noise Immune Mode. Oscillator warm-up required.
1 : quietMode
Always operate in Quiet Mode. No oscillator warm-up required.
2 : quietInStopWithWarmup
Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.
3 : quietInStopNoWarmup
Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit.
End of enumeration elements list.
WE : Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.
bits : 15 - 15 (1 bit)
Enumeration:
0 : inactive
Not active
1 : Pending
Active
End of enumeration elements list.
RTC Trim Register.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIM : RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.
bits : 0 - 7 (8 bit)
VBATTMR : VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.
bits : 8 - 31 (24 bit)
RTC Oscillator Control Register.
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLITER_EN : RTC Oscillator Filter Enable
bits : 0 - 0 (1 bit)
IBIAS_SEL : RTC Oscillator 4X Bias Current Select
bits : 1 - 1 (1 bit)
Enumeration:
0 : 2X
Selects 2X bias current for RTC oscillator
1 : 4X
Selects 4X bias current for RTC oscillator
End of enumeration elements list.
HYST_EN : RTC Oscillator Hysteresis Buffer Enable
bits : 2 - 2 (1 bit)
IBIAS_EN : RTC Oscillator Bias Current Enable
bits : 3 - 3 (1 bit)
BYPASS : RTC Crystal Bypass
bits : 4 - 4 (1 bit)
32KOUT : RTC 32kHz Square Wave Output
bits : 5 - 5 (1 bit)
RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTSS : RTC Sub-second Counter.
bits : 0 - 7 (8 bit)
Time-of-day Alarm.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAS : Time-of-day Alarm.
bits : 0 - 19 (20 bit)
RTC sub-second alarm. This register contains the reload value for the sub-second alarm.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSSA : This register contains the reload value for the sub-second alarm.
bits : 0 - 31 (32 bit)
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