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SDHC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SDMA

RESP0

RESP1

RESP2

RESP3

RESP[0]

BUFFER

PRESENT

HOST_CN_1

PWR

BLK_GAP

WAKEUP

CLK_CN

TO

SW_RESET

INT_STAT

ER_INT_STAT

RESP[1]

INT_EN

ER_INT_EN

INT_SIGNAL

ER_INT_SIGNAL

AUTO_CMD_ER

HOST_CN_2

BLK_SIZE

CFG_0

CFG_1

MAX_CURR_CFG

RESP[2]

FORCE_CMD

FORCE_EVENT_INT_STAT

ADMA_ER

ADMA_ADDR_0

ADMA_ADDR_1

BLK_CNT

PRESET_0

PRESET_1

PRESET_2

PRESET_3

RESP[3]

PRESET_4

PRESET_5

PRESET_6

PRESET_7

ARG_1

TRANS

CMD

SHARED_BUS

SLOT_INT

HOST_CN_VER


SDMA

SDMA System Address / Argument 2.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMA SDMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : SDMA System Address / Argument 2 of Auto CMD23.
bits : 0 - 31 (32 bit)


RESP0

Response 0 Register 0-15.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP0 RESP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_RESP

CMD_RESP : Command Response.
bits : 0 - 31 (32 bit)


RESP1

Response 0 Register 0-15.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP1 RESP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_RESP

CMD_RESP : Command Response.
bits : 0 - 31 (32 bit)


RESP2

Response 0 Register 0-15.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP2 RESP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_RESP

CMD_RESP : Command Response.
bits : 0 - 31 (32 bit)


RESP3

Response 0 Register 0-15.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP3 RESP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_RESP

CMD_RESP : Command Response.
bits : 0 - 31 (32 bit)


RESP[0]

Response 0 Register 0-15.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP[0] RESP[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_RESP

CMD_RESP : Command Response.
bits : 0 - 31 (32 bit)


BUFFER

Buffer Data Port.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFFER BUFFER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Buffer Data.
bits : 0 - 31 (32 bit)


PRESENT

Present State.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESENT PRESENT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD DAT DAT_LINE_ACTIVE RETUNING WRITE_TRANSFER READ_TRANSFER BUFFER_WRITE BUFFER_READ CARD_INSERTED CARD_STATE CARD_DETECT WP DAT_SIGNAL_LEVEL CMD_SIGNAL_LEVEL

CMD : Command Inhibit (CMD).
bits : 0 - 0 (1 bit)
access : read-only

DAT : Command Inhibit (DAT).
bits : 1 - 1 (1 bit)
access : read-only

DAT_LINE_ACTIVE : DAT Line Active.
bits : 2 - 2 (1 bit)
access : read-only

RETUNING : Re-Tuning Request.
bits : 3 - 3 (1 bit)
access : read-only

WRITE_TRANSFER : Write Transfer Active.
bits : 8 - 8 (1 bit)
access : read-only

READ_TRANSFER : Read Transfer Active.
bits : 9 - 9 (1 bit)
access : read-only

BUFFER_WRITE : Buffer Write Enable.
bits : 10 - 10 (1 bit)
access : read-only

BUFFER_READ : Buffer Read Enable.
bits : 11 - 11 (1 bit)
access : read-only

CARD_INSERTED : Card Inserted.
bits : 16 - 16 (1 bit)
access : read-only

CARD_STATE : Card State Stable.
bits : 17 - 17 (1 bit)
access : read-only

CARD_DETECT : Card Detect Pin Level.
bits : 18 - 18 (1 bit)
access : read-only

WP : Write Protect Switch Pin Level.
bits : 19 - 19 (1 bit)
access : read-only

DAT_SIGNAL_LEVEL : DAT[3:0] Line Signal Level.
bits : 20 - 23 (4 bit)

CMD_SIGNAL_LEVEL : CMD Line Signal Level.
bits : 24 - 24 (1 bit)


HOST_CN_1

Host Control 1.
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_CN_1 HOST_CN_1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 LED_CN DATA_TRANSFER_WIDTH HS_EN DMA_SELECT EXT_DATA_TRANSFER_WIDTH CARD_DETECT_TEST CARD_DETECT_SIGNAL

LED_CN : LED Control.
bits : 0 - 0 (1 bit)

DATA_TRANSFER_WIDTH : Data Transfer Width.
bits : 1 - 1 (1 bit)

HS_EN : High Speed Enable.
bits : 2 - 2 (1 bit)

DMA_SELECT : DMA Select.
bits : 3 - 4 (2 bit)

EXT_DATA_TRANSFER_WIDTH : Extended Data Transfer Width.
bits : 5 - 5 (1 bit)

CARD_DETECT_TEST : Card Detect Test Level.
bits : 6 - 6 (1 bit)

CARD_DETECT_SIGNAL : Card Detect Signal Selection.
bits : 7 - 7 (1 bit)


PWR

Power Control.
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR PWR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 BUS_POWER BUS_VOLT_SEL

BUS_POWER : SD Bus Power.
bits : 0 - 0 (1 bit)

BUS_VOLT_SEL : SD Bus Voltage Select.
bits : 1 - 3 (3 bit)


BLK_GAP

Block Gap Control.
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK_GAP BLK_GAP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STOP CONT READ_WAIT INTR

STOP : Stop At Block Gap Request.
bits : 0 - 0 (1 bit)

CONT : Continue Request.
bits : 1 - 1 (1 bit)

READ_WAIT : Read Wait Control.
bits : 2 - 2 (1 bit)

INTR : Interrupt At Block Gap.
bits : 3 - 3 (1 bit)


WAKEUP

Wakeup Control.
address_offset : 0x2B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKEUP WAKEUP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 CARD_INT CARD_INS CARD_REM

CARD_INT : Wakeup Event Enable On Card Interrupt.
bits : 0 - 0 (1 bit)

CARD_INS : Wakeup Event Enable On SD Card Insertion.
bits : 1 - 1 (1 bit)

CARD_REM : Wakeup Event Enable On SD Card Removal.
bits : 2 - 2 (1 bit)


CLK_CN

Clock Control.
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CN CLK_CN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTERNAL_CLK_EN INTERNAL_CLK_STABLE SD_CLK_EN CLK_GEN_SEL UPPER_SDCLK_FREQ_SEL SDCLK_FREQ_SEL

INTERNAL_CLK_EN : Internal Clock Enable.
bits : 0 - 0 (1 bit)

INTERNAL_CLK_STABLE : Internal Clock Stable.
bits : 1 - 1 (1 bit)
access : read-only

SD_CLK_EN : SD Clock Enable.
bits : 2 - 2 (1 bit)

CLK_GEN_SEL : Clock Generator Select.
bits : 5 - 5 (1 bit)
access : read-only

UPPER_SDCLK_FREQ_SEL : Upper Bits of SDCLK Frequency Select.
bits : 6 - 7 (2 bit)

SDCLK_FREQ_SEL : SDCLK Frequency Select.
bits : 8 - 15 (8 bit)


TO

Timeout Control.
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TO TO read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA_COUNT_VALUE

DATA_COUNT_VALUE : Data Timeout Counter Value.
bits : 0 - 2 (3 bit)


SW_RESET

Software Reset.
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_RESET SW_RESET read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RESET_ALL RESET_CMD RESET_DAT

RESET_ALL : Software Reset For All.
bits : 0 - 0 (1 bit)

RESET_CMD : Software Reset For CMD Line.
bits : 1 - 1 (1 bit)

RESET_DAT : Software Reset For DAT Line.
bits : 2 - 2 (1 bit)


INT_STAT

Normal Interrupt Status.
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STAT INT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_COMP TRANS_COMP BLK_GAP_EVENT DMA BUFF_WR_READY BUFF_RD_READY CARD_INSERTION CARD_REMOVAL CARD_INTR RETUNING ERR_INTR

CMD_COMP : Command Complete.
bits : 0 - 0 (1 bit)

TRANS_COMP : Transfer Complete.
bits : 1 - 1 (1 bit)

BLK_GAP_EVENT : Block Gap Event.
bits : 2 - 2 (1 bit)

DMA : DMA Interrupt.
bits : 3 - 3 (1 bit)

BUFF_WR_READY : Buffer Write Ready.
bits : 4 - 4 (1 bit)

BUFF_RD_READY : Buffer Read Ready.
bits : 5 - 5 (1 bit)

CARD_INSERTION : Card Insertion.
bits : 6 - 6 (1 bit)

CARD_REMOVAL : Card Removal.
bits : 7 - 7 (1 bit)

CARD_INTR : Card Interrupt.
bits : 8 - 8 (1 bit)

RETUNING : Re-Tuning Event.
bits : 12 - 12 (1 bit)

ERR_INTR : Error Interrupt.
bits : 15 - 15 (1 bit)


ER_INT_STAT

Error Interrupt Status.
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ER_INT_STAT ER_INT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_TO CMD_CRC CMD_END_BIT CMD_IDX DATA_TO DATA_CRC DATA_END_BIT CURRENT_LIMIT AUTO_CMD_12 ADMA DMA

CMD_TO : Command Timeout Error.
bits : 0 - 0 (1 bit)

CMD_CRC : Command CRC Error.
bits : 1 - 1 (1 bit)

CMD_END_BIT : Command End Bit Error.
bits : 2 - 2 (1 bit)

CMD_IDX : Command Index Error.
bits : 3 - 3 (1 bit)

DATA_TO : Data Timeout Error.
bits : 4 - 4 (1 bit)

DATA_CRC : Data CRC Error.
bits : 5 - 5 (1 bit)

DATA_END_BIT : Data End Bit Error.
bits : 6 - 6 (1 bit)

CURRENT_LIMIT : Current Limit Error.
bits : 7 - 7 (1 bit)

AUTO_CMD_12 : Auto CMD Error.
bits : 8 - 8 (1 bit)

ADMA : ADMA Error.
bits : 9 - 9 (1 bit)

DMA : DMA Error.
bits : 12 - 12 (1 bit)


RESP[1]

Response 0 Register 0-15.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP[1] RESP[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_RESP

CMD_RESP : Command Response.
bits : 0 - 31 (32 bit)


INT_EN

Normal Interrupt Status Enable.
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_EN INT_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_COMP TRANS_COMP BLK_GAP DMA BUFFER_WR BUFFER_RD CARD_INSERT CARD_REMOVAL CARD_INT RETUNING

CMD_COMP : Command Complete Status Enable.
bits : 0 - 0 (1 bit)

TRANS_COMP : Transfer Complete Status Enable.
bits : 1 - 1 (1 bit)

BLK_GAP : Block Gap Event Status Enable.
bits : 2 - 2 (1 bit)

DMA : DMA Interrupt Status Enable.
bits : 3 - 3 (1 bit)

BUFFER_WR : Buffer Write Ready Status Enable.
bits : 4 - 4 (1 bit)

BUFFER_RD : Buffer Read Ready Status Enable.
bits : 5 - 5 (1 bit)

CARD_INSERT : Card Insertion Status Enable.
bits : 6 - 6 (1 bit)

CARD_REMOVAL : Card Removal Status Enable.
bits : 7 - 7 (1 bit)

CARD_INT : Card Interrupt Status Enable.
bits : 8 - 8 (1 bit)

RETUNING : Re-Tuning Event Status Enable.
bits : 12 - 12 (1 bit)


ER_INT_EN

Error Interrupt Status Enable.
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ER_INT_EN ER_INT_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_TO CMD_CRC CMD_END_BIT CMD_IDX DATA_TO DATA_CRC DATA_END_BIT AUTO_CMD ADMA TUNING VENDOR

CMD_TO : Command Timeout Error Status Enable.
bits : 0 - 0 (1 bit)

CMD_CRC : Command CRC Error Status Enable.
bits : 1 - 1 (1 bit)

CMD_END_BIT : Command End Bit Error Status Enable.
bits : 2 - 2 (1 bit)

CMD_IDX : Command Index Error Status Enable.
bits : 3 - 3 (1 bit)

DATA_TO : Data Timeout Error Status Enable.
bits : 4 - 4 (1 bit)

DATA_CRC : Data CRC Error Status Enable.
bits : 5 - 5 (1 bit)

DATA_END_BIT : Data End Bit Error Status Enable.
bits : 6 - 6 (1 bit)

AUTO_CMD : Auto CMD Error Status Enable.
bits : 8 - 8 (1 bit)

ADMA : ADMA Error Status Enable.
bits : 9 - 9 (1 bit)

TUNING : Tuning Error Status Enable.
bits : 10 - 10 (1 bit)

VENDOR : Vendor Specific Error Status Enable.
bits : 12 - 12 (1 bit)


INT_SIGNAL

Normal Interrupt Signal Enable.
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_SIGNAL INT_SIGNAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_COMP TRANS_COMP BLK_GAP DMA BUFFER_WR BUFFER_RD CARD_INSERT CARD_REMOVAL CARD_INT RETUNING

CMD_COMP : Command Complete Signal Enable.
bits : 0 - 0 (1 bit)

TRANS_COMP : Transfer Complete Signal Enable.
bits : 1 - 1 (1 bit)

BLK_GAP : Block Gap Event Signal Enable.
bits : 2 - 2 (1 bit)

DMA : DMA Interrupt Signal Enable.
bits : 3 - 3 (1 bit)

BUFFER_WR : Buffer Write Ready Signal Enable.
bits : 4 - 4 (1 bit)

BUFFER_RD : Buffer Read Ready Signal Enable.
bits : 5 - 5 (1 bit)

CARD_INSERT : Card Insertion Signal Enable.
bits : 6 - 6 (1 bit)

CARD_REMOVAL : Card Removal Signal Enable.
bits : 7 - 7 (1 bit)

CARD_INT : Card Interrupt Signal Enable.
bits : 8 - 8 (1 bit)

RETUNING : Re-Tuning Event Signal Enable.
bits : 12 - 12 (1 bit)


ER_INT_SIGNAL

Error Interrupt Signal Enable.
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ER_INT_SIGNAL ER_INT_SIGNAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_TO CMD_CRC CMD_END_BIT CMD_IDX DATA_TO DATA_CRC DATA_END_BIT CURR_LIM AUTO_CMD ADMA TUNING TAR_RESP

CMD_TO : Command Timeout Error Signal Enable.
bits : 0 - 0 (1 bit)

CMD_CRC : Command CRC Error Signal Enable.
bits : 1 - 1 (1 bit)

CMD_END_BIT : Command End Bit Error Signal Enable.
bits : 2 - 2 (1 bit)

CMD_IDX : Command Index Error Signal Enable.
bits : 3 - 3 (1 bit)

DATA_TO : Data Timeout Error Signal Enable.
bits : 4 - 4 (1 bit)

DATA_CRC : Data CRC Error Signal Enable.
bits : 5 - 5 (1 bit)

DATA_END_BIT : Data End Bit Error Signal Enable.
bits : 6 - 6 (1 bit)

CURR_LIM : Current Limit Error Signal Enable.
bits : 7 - 7 (1 bit)

AUTO_CMD : Auto CMD Error Signal Enable.
bits : 8 - 8 (1 bit)

ADMA : ADMA Error Signal Enable.
bits : 9 - 9 (1 bit)

TUNING : Tuning Error Signal Enable.
bits : 10 - 10 (1 bit)

TAR_RESP : Target Response Error Signal Enable.
bits : 12 - 12 (1 bit)


AUTO_CMD_ER

Auto CMD Error Status.
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUTO_CMD_ER AUTO_CMD_ER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOT_EXCUTED TO CRC END_BIT INDEX NOT_ISSUED

NOT_EXCUTED : Auto CMD12 Not Executed.
bits : 0 - 0 (1 bit)

TO : Auto CMD Timeout Error.
bits : 1 - 1 (1 bit)

CRC : Auto CMD CRC Error.
bits : 2 - 2 (1 bit)

END_BIT : Auto CMD End Bit Error.
bits : 3 - 3 (1 bit)

INDEX : Auto CMD Index Error.
bits : 4 - 4 (1 bit)

NOT_ISSUED : Command Not Issued By Auto CMD12 Error.
bits : 7 - 7 (1 bit)


HOST_CN_2

Host Control 2.
address_offset : 0x3E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_CN_2 HOST_CN_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UHS SIGNAL_V1_8 DRIVER_STRENGTH EXCUTE SAMPLING_CLK ASYNCH_INT PRESET_VAL_EN

UHS : UHS Mode Select.
bits : 0 - 1 (2 bit)

SIGNAL_V1_8 : 1.8V Signaling Enable.
bits : 3 - 3 (1 bit)

DRIVER_STRENGTH : Driver Strength Select.
bits : 4 - 5 (2 bit)

EXCUTE : Execute Tuning.
bits : 6 - 6 (1 bit)

SAMPLING_CLK : Sampling Clock Select.
bits : 7 - 7 (1 bit)

ASYNCH_INT : Asynchronous Interrupt Enable.
bits : 14 - 14 (1 bit)

PRESET_VAL_EN : Preset Value Enable.
bits : 15 - 15 (1 bit)


BLK_SIZE

Block Size.
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK_SIZE BLK_SIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRANS HOST_BUFF

TRANS : Transfer Block Size.
bits : 0 - 11 (12 bit)

HOST_BUFF : Host SDMA Buffer Boundary.
bits : 12 - 14 (3 bit)


CFG_0

Capabilities 0-31.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CFG_0 CFG_0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_CLK_FREQ TO_CLK_UNIT CLK_FREQ MAX_BLK_LEN BIT_8 ADMA2 HS SDMA SUSPEND V3_3 V3_0 V1_8 BIT_64_SYS_BUS ASYNC_INT SLOT_TYPE

TO_CLK_FREQ : Timeout Clock Frequency.
bits : 0 - 5 (6 bit)
access : read-only

TO_CLK_UNIT : Timeout Clock Unit.
bits : 7 - 7 (1 bit)
access : read-only

CLK_FREQ : Base Clock Frequency For SD Clock.
bits : 8 - 15 (8 bit)
access : read-only

MAX_BLK_LEN : Max Block Length.
bits : 16 - 17 (2 bit)
access : read-only

BIT_8 : 8-bit Support for Embedded Device.
bits : 18 - 18 (1 bit)
access : read-only

ADMA2 : ADMA2 Support.
bits : 19 - 19 (1 bit)
access : read-only

HS : High Speed Support.
bits : 21 - 21 (1 bit)
access : read-only

SDMA : SDMA Support.
bits : 22 - 22 (1 bit)
access : read-only

SUSPEND : Suspend/Resume Support.
bits : 23 - 23 (1 bit)
access : read-only

V3_3 : Voltage Support 3.3V.
bits : 24 - 24 (1 bit)
access : read-only

V3_0 : Voltage Support 3.0V.
bits : 25 - 25 (1 bit)
access : read-only

V1_8 : Voltage Support 1.8V.
bits : 26 - 26 (1 bit)
access : read-only

BIT_64_SYS_BUS : 64-bit System Bus Support.
bits : 28 - 28 (1 bit)
access : read-only

ASYNC_INT : Asynchronous Interrupt Support.
bits : 29 - 29 (1 bit)
access : read-only

SLOT_TYPE : Slot Type.
bits : 30 - 31 (2 bit)
access : read-only


CFG_1

Capabilities 32-63.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CFG_1 CFG_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDR50 SDR104 DDR50 DRIVER_A DRIVER_C DRIVER_D TIMER_CNT_TUNING TUNING_SDR50 RETUNING CLK_MULTI

SDR50 : SDR50 Support.
bits : 0 - 0 (1 bit)
access : read-only

SDR104 : SDR104 Support.
bits : 1 - 0 (0 bit)
access : read-only

DDR50 : DDR50 Support.
bits : 2 - 2 (1 bit)
access : read-only

DRIVER_A : Driver Type A Support.
bits : 4 - 4 (1 bit)
access : read-only

DRIVER_C : Driver Type C Support.
bits : 5 - 5 (1 bit)
access : read-only

DRIVER_D : Driver Type D Support.
bits : 6 - 6 (1 bit)
access : read-only

TIMER_CNT_TUNING : Timer Count for Re-Tuning.
bits : 8 - 11 (4 bit)
access : read-only

TUNING_SDR50 : Use Tuning for SDR50.
bits : 13 - 13 (1 bit)
access : read-only

RETUNING : Re-Tuning Modes.
bits : 14 - 15 (2 bit)
access : read-only

CLK_MULTI : Clock Multiplier.
bits : 16 - 23 (8 bit)
access : read-only


MAX_CURR_CFG

Maximum Current Capabilities.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MAX_CURR_CFG MAX_CURR_CFG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 V3_3 V3_0 V1_8

V3_3 : Maximum Current for 3.3V.
bits : 0 - 7 (8 bit)
access : read-only

V3_0 : Maximum Current for 3.0V.
bits : 8 - 15 (8 bit)
access : read-only

V1_8 : Maximum Current for 1.8V.
bits : 16 - 23 (8 bit)
access : read-only


RESP[2]

Response 0 Register 0-15.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP[2] RESP[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_RESP

CMD_RESP : Command Response.
bits : 0 - 31 (32 bit)


FORCE_CMD

Force Event for Auto CMD Error Status.
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

FORCE_CMD FORCE_CMD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NOT_EXCU TO CRC END_BIT INDEX NOT_ISSUED

NOT_EXCU : Force Event for Auto CMD12 Not Executed.
bits : 0 - 0 (1 bit)
access : write-only

TO : Force Event for Auto CMD Timeout Error.
bits : 1 - 1 (1 bit)
access : write-only

CRC : Force Event for Auto CMD CRC Error.
bits : 2 - 2 (1 bit)
access : write-only

END_BIT : Force Event for Auto CMD End Bit Error.
bits : 3 - 3 (1 bit)
access : write-only

INDEX : Force Event for Auto CMD Index Error.
bits : 4 - 4 (1 bit)
access : write-only

NOT_ISSUED : Force Event for Command Not Issued By Auto CMD12 Error.
bits : 7 - 7 (1 bit)
access : write-only


FORCE_EVENT_INT_STAT

Force Event for Error Interrupt Status.
address_offset : 0x52 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FORCE_EVENT_INT_STAT FORCE_EVENT_INT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_TO CMD_CRC CMD_END_BIT CMD_INDEX DATA_TO DATA_CRC DATA_END_BIT CURR_LIMIT AUTO_CMD ADMA VENDOR

CMD_TO : Force Event for Command Timeout Error.
bits : 0 - 0 (1 bit)
access : read-only

CMD_CRC : Force Event for Command CRC Error.
bits : 1 - 1 (1 bit)
access : read-only

CMD_END_BIT : Force Event for Command End Bit Error.
bits : 2 - 2 (1 bit)
access : read-only

CMD_INDEX : Force Event for Command Index Error.
bits : 3 - 3 (1 bit)
access : read-only

DATA_TO : Force Event for Data Timeout Error.
bits : 4 - 4 (1 bit)
access : read-only

DATA_CRC : Force Event for Data CRC Error.
bits : 5 - 5 (1 bit)
access : read-only

DATA_END_BIT : Force Event for Data End Bit Error.
bits : 6 - 6 (1 bit)
access : read-only

CURR_LIMIT : Force Event for Current Limit Error.
bits : 7 - 7 (1 bit)
access : read-only

AUTO_CMD : Force Event for Auto CMD Error.
bits : 8 - 8 (1 bit)
access : read-only

ADMA : Force Event for ADMA Error.
bits : 9 - 9 (1 bit)

VENDOR : Force Event for Vendor Specific Error Status.
bits : 12 - 14 (3 bit)
access : write-only


ADMA_ER

ADMA Error Status.
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADMA_ER ADMA_ER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 STATE LEN_MISMATCH

STATE : ADMA Error State.
bits : 0 - 1 (2 bit)

LEN_MISMATCH : ADMA Length Mismatch Error.
bits : 2 - 2 (1 bit)


ADMA_ADDR_0

ADMA System Address 0-31.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADMA_ADDR_0 ADMA_ADDR_0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ADMA System Address Part 1 (part 2 is ADMA_ADDR_1).
bits : 0 - 31 (32 bit)


ADMA_ADDR_1

ADMA System Address 32-63.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADMA_ADDR_1 ADMA_ADDR_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ADMA System Address Part 1 (part 2 is ADMA_ADDR_1).
bits : 0 - 31 (32 bit)


BLK_CNT

Block Count.
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK_CNT BLK_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Blocks Count For Current Transfer.
bits : 0 - 15 (16 bit)


PRESET_0

Preset Value for Initialization.
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESET_0 PRESET_0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCLK_FREQ CLK_GEN DRIVER_STRENGTH

SDCLK_FREQ : SDCLK Frequency Select Value.
bits : 0 - 9 (10 bit)
access : read-only

CLK_GEN : Clock Generator Select Value.
bits : 10 - 10 (1 bit)
access : read-only

DRIVER_STRENGTH : Driver Strength Select Value.
bits : 14 - 15 (2 bit)
access : read-only


PRESET_1

Preset Value for Default Speed.
address_offset : 0x62 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESET_1 PRESET_1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCLK_FREQ CLK_GEN DRIVER_STRENGTH

SDCLK_FREQ : SDCLK Frequency Select Value.
bits : 0 - 9 (10 bit)
access : read-only

CLK_GEN : Clock Generator Select Value.
bits : 10 - 10 (1 bit)
access : read-only

DRIVER_STRENGTH : Driver Strength Select Value.
bits : 14 - 15 (2 bit)
access : read-only


PRESET_2

Preset Value for High Speed.
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESET_2 PRESET_2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCLK_FREQ CLK_GEN DRIVER_STRENGTH

SDCLK_FREQ : SDCLK Frequency Select Value.
bits : 0 - 9 (10 bit)
access : read-only

CLK_GEN : Clock Generator Select Value.
bits : 10 - 10 (1 bit)
access : read-only

DRIVER_STRENGTH : Driver Strength Select Value.
bits : 14 - 15 (2 bit)
access : read-only


PRESET_3

Preset Value for SDR12.
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESET_3 PRESET_3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCLK_FREQ CLK_GEN DRIVER_STRENGTH

SDCLK_FREQ : SDCLK Frequency Select Value.
bits : 0 - 9 (10 bit)
access : read-only

CLK_GEN : Clock Generator Select Value.
bits : 10 - 10 (1 bit)
access : read-only

DRIVER_STRENGTH : Driver Strength Select Value.
bits : 14 - 15 (2 bit)
access : read-only


RESP[3]

Response 0 Register 0-15.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESP[3] RESP[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD_RESP

CMD_RESP : Command Response.
bits : 0 - 31 (32 bit)


PRESET_4

Preset Value for SDR25.
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESET_4 PRESET_4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCLK_FREQ CLK_GEN DRIVER_STRENGTH

SDCLK_FREQ : SDCLK Frequency Select Value.
bits : 0 - 9 (10 bit)
access : read-only

CLK_GEN : Clock Generator Select Value.
bits : 10 - 10 (1 bit)
access : read-only

DRIVER_STRENGTH : Driver Strength Select Value.
bits : 14 - 15 (2 bit)
access : read-only


PRESET_5

Preset Value for SDR50.
address_offset : 0x6A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESET_5 PRESET_5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCLK_FREQ CLK_GEN DRIVER_STRENGTH

SDCLK_FREQ : SDCLK Frequency Select Value.
bits : 0 - 9 (10 bit)
access : read-only

CLK_GEN : Clock Generator Select Value.
bits : 10 - 10 (1 bit)
access : read-only

DRIVER_STRENGTH : Driver Strength Select Value.
bits : 14 - 15 (2 bit)
access : read-only


PRESET_6

Preset Value for SDR104.
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESET_6 PRESET_6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCLK_FREQ CLK_GEN DRIVER_STRENGTH

SDCLK_FREQ : SDCLK Frequency Select Value.
bits : 0 - 9 (10 bit)
access : read-only

CLK_GEN : Clock Generator Select Value.
bits : 10 - 10 (1 bit)
access : read-only

DRIVER_STRENGTH : Driver Strength Select Value.
bits : 14 - 15 (2 bit)
access : read-only


PRESET_7

Preset Value for DDR50.
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PRESET_7 PRESET_7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCLK_FREQ CLK_GEN DRIVER_STRENGTH

SDCLK_FREQ : SDCLK Frequency Select Value.
bits : 0 - 9 (10 bit)
access : read-only

CLK_GEN : Clock Generator Select Value.
bits : 10 - 10 (1 bit)
access : read-only

DRIVER_STRENGTH : Driver Strength Select Value.
bits : 14 - 15 (2 bit)
access : read-only


ARG_1

Argument 1.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARG_1 ARG_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMD

CMD : Command Argument 1.
bits : 0 - 31 (32 bit)


TRANS

Transfer Mode.
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRANS TRANS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_EN BLK_CNT_EN AUTO_CMD_EN READ_WRITE MULTI

DMA_EN : DMA Enable.
bits : 0 - 0 (1 bit)

Enumeration: enable

1 : dma_transfer

None

0 : non_dma_transfer

None

End of enumeration elements list.

BLK_CNT_EN : Block Count Enable.
bits : 1 - 1 (1 bit)

Enumeration: count

1 : enable

None

0 : disable

None

End of enumeration elements list.

AUTO_CMD_EN : Auto CMD Enable.
bits : 2 - 3 (2 bit)

Enumeration: CMD

0 : disable

None

1 : cmd12

None

2 : cmd23

None

End of enumeration elements list.

READ_WRITE : Data Transfer Direction Select.
bits : 4 - 4 (1 bit)

Enumeration: read

1 : read

None

0 : write

None

End of enumeration elements list.

MULTI : Multi / Single Block Select.
bits : 5 - 5 (1 bit)

Enumeration: multi

1 : enable

None

0 : disable

None

End of enumeration elements list.


CMD

Command.
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESP_TYPE CRC_CHK_EN IDX_CHK_EN DATA_PRES_SEL TYPE IDX

RESP_TYPE : Response Type Select.
bits : 0 - 1 (2 bit)

CRC_CHK_EN : Command CRC Check Enable.
bits : 3 - 3 (1 bit)

IDX_CHK_EN : Command Index Check Enable.
bits : 4 - 4 (1 bit)

DATA_PRES_SEL : Data Present Select.
bits : 5 - 5 (1 bit)

TYPE : Command Type.
bits : 6 - 7 (2 bit)

IDX : Command Index.
bits : 8 - 13 (6 bit)


SHARED_BUS

Shared Bus Control.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHARED_BUS SHARED_BUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SLOT_INT

Slot Interrupt Status.
address_offset : 0xFC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SLOT_INT SLOT_INT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SIGNALS

INT_SIGNALS : Interrupt Signal For Each Slot.
bits : 0 - 0 (1 bit)
access : read-only


HOST_CN_VER

Host Controller Version.
address_offset : 0xFE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HOST_CN_VER HOST_CN_VER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPEC_VER VEND_VER

SPEC_VER : Specification Version Number.
bits : 0 - 7 (8 bit)

VEND_VER : Vendor Version Number.
bits : 8 - 15 (8 bit)



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