Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Configuration Register.
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SSEL : Slaves Select.
bits : 0 - 2 (3 bit)
Enumeration:
0 : Slave_0
Slave 0 is selected.
1 : Slave_1
Slave 1 is selected.
End of enumeration elements list.
MODE : Defines SPI Mode, Only valid values are 0 and 3.
bits : 4 - 5 (2 bit)
Enumeration:
0 : SPIX_Mode_0
SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0.
3 : SPIX_Mode_3
SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1.
End of enumeration elements list.
PAGE_SIZE : Page Size.
bits : 6 - 7 (2 bit)
Enumeration:
0 : 4_bytes
4 bytes.
1 : 8_bytes
8 bytes.
2 : 16_bytes
16 bytes.
3 : 32_bytes
32 bytes.
End of enumeration elements list.
HI_CLK : SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high.
bits : 8 - 11 (4 bit)
Enumeration:
0 : 16_SCLK
16 system clocks.
End of enumeration elements list.
LO_CLK : SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low.
bits : 12 - 15 (4 bit)
Enumeration:
0 : 16_SCLK
16 system clocks.
End of enumeration elements list.
SS_ACT : Slaves Select Activate Timing.
bits : 16 - 17 (2 bit)
Enumeration:
0 : 0_CLKS
0 sytem clocks.
1 : 2_CLKS
2 sytem clocks.
2 : 4_CLKS
4 sytem clocks.
3 : 8_CLKS
8 sytem clocks.
End of enumeration elements list.
SS_INACT : Slaves Select Inactive Timing.
bits : 18 - 19 (2 bit)
Enumeration:
0 : 4_CLKS
4 sytem clocks.
1 : 6_CLKS
6 sytem clocks.
2 : 8_CLKS
8 sytem clocks.
3 : 12_CLKS
12 sytem clocks.
End of enumeration elements list.
SPIX Controller Special Control Register.
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SCLKINH3 : SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams.
bits : 16 - 16 (1 bit)
Enumeration:
0 : EN
Allow trailing SCLK low pulse prior to Slave Select de-assertion.
1 : DIS
Inhibit trailing SCLK low pulse prior to Slave Select de-assertion.
End of enumeration elements list.
SPIX Controller Interrupt Status Register.
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_STALLED : Transaction Stalled Interrupt Flag.
bits : 0 - 0 (1 bit)
Enumeration:
0 : CLR
Normal FIFO Transaction.
1 : SET
Stalled FIFO Transaction.
End of enumeration elements list.
RX_STALLED : Results Stalled Interrupt Flag.
bits : 1 - 1 (1 bit)
Enumeration:
0 : CLR
Normal FIFO Operation.
1 : SET
Stalled FIFO.
End of enumeration elements list.
TX_READY : Transaction Ready Interrupt Status.
bits : 2 - 2 (1 bit)
Enumeration:
0 : CLR
FIFO Transaction not ready.
1 : SET
FIFO Transaction ready.
End of enumeration elements list.
RX_DONE : Results Done Interrupt Status.
bits : 3 - 3 (1 bit)
Enumeration:
0 : CLR
Results FIFO ready.
1 : SET
Results FIFO Not ready.
End of enumeration elements list.
TX_FIFO_AE : Transaction FIFO Almost Empty Flag.
bits : 4 - 4 (1 bit)
Enumeration:
0 : CLR
Transaction FIFO not Almost Empty.
1 : SET
Transaction FIFO Almost Empty.
End of enumeration elements list.
RX_FIFO_AF : Results FIFO Almost Full Flag.
bits : 5 - 5 (1 bit)
Enumeration:
0 : CLR
Results FIFO level below the Almost Full level.
1 : SET
Results FIFO level at Almost Full level.
End of enumeration elements list.
SPIX Controller Interrupt Enable Register.
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_STALLED : Transaction Stalled Interrupt Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : EN
Disable Transaction Stalled Interrupt.
1 : DIS
Enable Transaction Stalled Interrupt.
End of enumeration elements list.
RX_STALLED : Results Stalled Interrupt Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : EN
Disable Results Stalled Interrupt.
1 : DIS
Enable Results Stalled Interrupt.
End of enumeration elements list.
TX_READY : Transaction Ready Interrupt Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : EN
Disable FIFO Transaction Ready Interrupt.
1 : DIS
Enable FIFO Transaction Ready Interrupt.
End of enumeration elements list.
RX_DONE : Results Done Interrupt Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : EN
Disable Results Done Interrupt.
1 : DIS
Enable Results Done Interrupt.
End of enumeration elements list.
TX_FIFO_AE : Transaction FIFO Almost Empty Interrupt Enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : EN
Disable Transaction FIFO Almost Empty Interrupt.
1 : DIS
Enable Transaction FIFO Almost Empty Interrupt.
End of enumeration elements list.
RX_FIFO_AF : Results FIFO Almost Full Interrupt Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : EN
Disable Results FIFO Almost Full Interrupt.
1 : DIS
Enable Results FIFO Almost Full Interrupt.
End of enumeration elements list.
SPIX Controller Slave Select Polarity Register.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SS_POLARITY : Slave Select Polarity.
bits : 0 - 0 (1 bit)
Enumeration:
0 : lo
Active Low.
1 : hi
Active High.
End of enumeration elements list.
SPIX Controller General Controller Register.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : SPI Master enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable SPI Master, putting a reset state.
1 : en
Enable SPI Master for processing transactions.
End of enumeration elements list.
TX_FIFO_EN : Transaction FIFO Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis_txfifo
Disable Transaction FIFO.
1 : en_txfifo
Enable Transaction FIFO.
End of enumeration elements list.
RX_FIFO_EN : Result FIFO Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : DIS_RXFIFO
Disable Result FIFO.
1 : EN_RXFIFO
Enable Result FIFO.
End of enumeration elements list.
BBMODE : Bit-Bang Mode.
bits : 3 - 3 (1 bit)
Enumeration:
0 : dis
Disable Bit-Bang Mode.
1 : en
Enable Bit-Bang Mode.
End of enumeration elements list.
SSDR : This bits reflects the state of the currently selected slave select.
bits : 4 - 4 (1 bit)
Enumeration:
0 : output0
Selected Slave select output = 0.
1 : output1
Selected Slave select output = 1.
End of enumeration elements list.
SCLK_DR : SSCLK Drive and State.
bits : 6 - 6 (1 bit)
Enumeration:
0 : SCLK_0
SCLK is 0.
1 : SCLK_1
SCLK is 1.
End of enumeration elements list.
SDIO_DATA_IN : SDIO Input Data Value.
bits : 8 - 11 (4 bit)
Enumeration:
0 : SDIO0
SDIO[0]
1 : SDIO1
SDIO[1]
2 : SDIO2
SDIO[2]
3 : SDIO3
SDIO[3]
End of enumeration elements list.
BB_DATA : No description available.
bits : 12 - 15 (4 bit)
Enumeration:
0 : SDIO0
SDIO[0]
1 : SDIO1
SDIO[1]
2 : SDIO2
SDIO[2]
3 : SDIO3
SDIO[3]
End of enumeration elements list.
BB_DATA_OUT_EN : Bit Bang SDIO Output Enable.
bits : 16 - 19 (4 bit)
Enumeration:
0 : SDIO0
SDIO[0]
1 : SDIO1
SDIO[1]
2 : SDIO2
SDIO[2]
3 : SDIO3
SDIO[3]
End of enumeration elements list.
SCLK_FB : Enable SCLK Feedback Mode.
bits : 24 - 24 (1 bit)
Enumeration:
0 : Dis
None
1 : En
None
End of enumeration elements list.
SPIX Controller FIFO Control and Status Register.
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_FIFO_AE_LVL : Transaction FIFO Almost Empty Level.
bits : 0 - 3 (4 bit)
TX_FIFO_CNT : Transaction FIFO Used.
bits : 8 - 12 (5 bit)
RX_FIFO_AF_LVL : Results FIFO Almost Full Level.
bits : 16 - 20 (5 bit)
RX_FIFO_CNT : Result FIFO Used.
bits : 24 - 29 (6 bit)
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