\n

SPIXC_FIFO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

TX_8

TX_16

TX_32

RX_8

RX_16

RX_32


TX_8

SPI TX FIFO 8-Bit Write
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TX_8 TX_8 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

TX_16

SPI TX FIFO 16-Bit Write
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : TX_8
reset_Mask : 0x0

TX_16 TX_16 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TX_32

SPI TX FIFO 32-Bit Write
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : TX_8
reset_Mask : 0x0

TX_32 TX_32 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RX_8

SPI RX FIFO 8-Bit Access
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RX_8 RX_8 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0

RX_16

SPI RX FIFO 16-Bit Access
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : RX_8
reset_Mask : 0x0

RX_16 RX_16 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RX_32

SPI RX FIFO 32-Bit Access
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : RX_8
reset_Mask : 0x0

RX_32 RX_32 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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