Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SPIX Configuration Register.
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MODE : Defines SPI Mode, Only valid values are 0 and 3.
bits : 0 - 1 (2 bit)
Enumeration:
0 : SCLK_HI_SAMPLE_RISING
Description not available.
3 : SCLK_LO_SAMPLE_FAILLING
Description not available.
End of enumeration elements list.
SSPOL : Slave Select Polarity.
bits : 2 - 2 (1 bit)
Enumeration:
0 : ACTIVE_HIGH
Slave Select is Active High.
1 : ACTIVE_LOW
Slave Select is Active Low.
End of enumeration elements list.
SSEL : Slave Select. Only valid value is zero.
bits : 4 - 6 (3 bit)
LO_CLK : Number of system clocks that SCLK will be low when SCLK pulses are generated.
bits : 8 - 11 (4 bit)
HI_CLK : Number of system clocks that SCLK will be high when SCLK pulses are generated.
bits : 12 - 15 (4 bit)
SSACT : Slave Select Active Timing.
bits : 16 - 17 (2 bit)
Enumeration:
0 : off
0 system clocks.
1 : for_2_mod_clk
2 System clocks.
2 : for_4_mod_clk
4 System clocks.
3 : for_8_mod_clk
8 System clocks.
End of enumeration elements list.
SSIACT : Slave Select Inactive Timing.
bits : 18 - 19 (2 bit)
Enumeration:
0 : for_1_mod_clk
1 system clocks.
1 : for_3_mod_clk
3 System clocks.
2 : for_5_mod_clk
5 System clocks.
3 : for_9_mod_clk
9 System clocks.
End of enumeration elements list.
SPIX Feedback Control Register.
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FB_EN : Enable SCLK feedback mode.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable SCLK feedback mode.
1 : en
Enable SCLK feedback mode.
End of enumeration elements list.
INVERT_EN : Invert SCLK in feedback mode.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable Invert SCLK feedback mode.
1 : en
Enable Invert SCLK feedback mode.
End of enumeration elements list.
IGNORE_CLKS : Number of clocks to ignore after SS asertion prior to reading data.
bits : 4 - 9 (6 bit)
IGNORE_CLKS_NO_CMD : Number of clocks to ignore after SS asertion prior to reading data when a read command is not explicitly sent.
bits : 12 - 17 (6 bit)
SPIX IO Control Register.
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SCLK_DS : SCLK drive Strength. This bit controls the drive strength on the SCLK pin.
bits : 0 - 0 (1 bit)
Enumeration:
0 : Low
Low drive strength.
1 : High
High drive strength.
End of enumeration elements list.
SS_DS : Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin.
bits : 1 - 1 (1 bit)
Enumeration:
0 : Low
Low drive strength.
1 : High
High drive strength.
End of enumeration elements list.
SDIO_DS : SDIO Drive Strength. This bit controls the drive strength of all SDIO pins.
bits : 2 - 2 (1 bit)
Enumeration:
0 : Low
Low drive strength.
1 : High
High drive strength.
End of enumeration elements list.
PU_PD_CTRL : IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins.
bits : 3 - 4 (2 bit)
Enumeration:
0 : tri_state
Tristate.
1 : Pull_Up
Pull-Up.
2 : Pull_down
Pull-Down.
End of enumeration elements list.
SPIX Memory Security Control Register.
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DECEN : Decryption Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable decryption of SPIX data.
1 : en
Enable decryption of SPIX data.
End of enumeration elements list.
SPIX Fetch Control Register.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMDVAL : Command Value sent to target to initiate fetching from SPI flash.
bits : 0 - 7 (8 bit)
CMD_WIDTH : Command Width. Number of data I/O used to send commands.
bits : 8 - 9 (2 bit)
Enumeration:
0 : Single
Single SDIO.
1 : Dual_IO
Dual SDIO.
2 : Quad_IO
Quad SDIO.
3 : Invalid
Invalid.
End of enumeration elements list.
ADDR_WIDTH : Address Width. Number of data I/O used to send address, and mode/dummy clocks.
bits : 10 - 11 (2 bit)
Enumeration:
0 : Single
Single SDIO.
1 : Dual_IO
Dual SDIO.
2 : Quad_IO
Quad SDIO.
3 : Invalid
Invalid.
End of enumeration elements list.
DATA_WIDTH : Data Width. Number of data I/O used to receive data.
bits : 12 - 13 (2 bit)
Enumeration:
0 : Single
Single SDIO.
1 : Dual_IO
Dual SDIO.
2 : Quad_IO
Quad SDIO.
3 : Invalid
Invalid.
End of enumeration elements list.
FOUR_BYTE_ADDR : Four Byte Address Mode. Enables 4-byte Flash Address Mode.
bits : 16 - 16 (1 bit)
Enumeration:
0 : 3
3 Byte Address Mode.
1 : 4
4 Byte Address Mode.
End of enumeration elements list.
SPIX Mode Control Register.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MDCLK : Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch.
bits : 0 - 3 (4 bit)
NO_CMD : No Command Mode.
bits : 8 - 8 (1 bit)
Enumeration:
0 : always
Send read command every time SPI transaction is initiated.
1 : once
Send read command only once. NO read command in subsequent SPI transactions.
End of enumeration elements list.
SPIX Mode Data Register.
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Mode Data. Specifies the data to send with the Dummy/Mode clocks.
bits : 0 - 15 (16 bit)
OUT_EN : Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA.
bits : 16 - 31 (16 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.