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SPI17Y

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DATA32

DATA16[0]

DATA8[0]

DATA160

DATA80

DATA8[1]

DATA81

SS_TIME

CLK_CFG

DMA

DATA16[1]

DATA161

DATA82

INT_FL

INT_EN

WAKE_FL

WAKE_EN

DATA8[2]

DATA83

STAT

CTRL0

DATA8[3]

CTRL1

CTRL2


DATA32

Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA32 DATA32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 31 (32 bit)


DATA16[0]

Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA16[0] DATA16[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 15 (16 bit)


DATA8[0]

Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA8[0] DATA8[0] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)


DATA160

Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA160 DATA160 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 15 (16 bit)


DATA80

Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA80 DATA80 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)


DATA8[1]

Register for reading and writing the FIFO.
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA8[1] DATA8[1] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)


DATA81

Register for reading and writing the FIFO.
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA81 DATA81 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)


SS_TIME

Register for controlling SPI peripheral/Slave Select Timing.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SS_TIME SS_TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRE POST INACT

PRE : Slave Select Pre delay 1.
bits : 0 - 7 (8 bit)

Enumeration:

0 : 256

256 system clocks between SS active and first serial clock edge.

End of enumeration elements list.

POST : Slave Select Post delay 2.
bits : 8 - 15 (8 bit)

Enumeration:

0 : 256

256 system clocks between last serial clock edge and SS inactive.

End of enumeration elements list.

INACT : Slave Select Inactive delay.
bits : 16 - 23 (8 bit)

Enumeration:

0 : 256

256 system clocks between transactions.

End of enumeration elements list.


CLK_CFG

Register for controlling SPI clock rate.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_CFG CLK_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LO HI SCALE

LO : Low duty cycle control. In timer mode, reload[7:0].
bits : 0 - 7 (8 bit)

Enumeration:

0 : Dis

Duty cycle control of serial clock generation is disabled.

End of enumeration elements list.

HI : High duty cycle control. In timer mode, reload[15:8].
bits : 8 - 15 (8 bit)

Enumeration:

0 : Dis

Duty cycle control of serial clock generation is disabled.

End of enumeration elements list.

SCALE : System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.
bits : 16 - 19 (4 bit)


DMA

Register for controlling DMA.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_FIFO_LEVEL TX_FIFO_EN TX_FIFO_CLEAR TX_FIFO_CNT TX_DMA_EN RX_FIFO_LEVEL RX_FIFO_EN RX_FIFO_CLEAR RX_FIFO_CNT RX_DMA_EN

TX_FIFO_LEVEL : Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.
bits : 0 - 4 (5 bit)

TX_FIFO_EN : Transmit FIFO enabled for SPI transactions.
bits : 6 - 6 (1 bit)

Enumeration:

0 : dis

Transmit FIFO is not enabled.

1 : en

Transmit FIFO is enabled.

End of enumeration elements list.

TX_FIFO_CLEAR : Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. .
bits : 7 - 7 (1 bit)

Enumeration:

1 : CLEAR

Clear the Transmit FIFO, clears any pending TX FIFO status.

End of enumeration elements list.

TX_FIFO_CNT : Count of entries in TX FIFO.
bits : 8 - 13 (6 bit)
access : read-only

TX_DMA_EN : TX DMA Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DIS

TX DMA requests are disabled, andy pending DMA requests are cleared.

1 : en

TX DMA requests are enabled.

End of enumeration elements list.

RX_FIFO_LEVEL : Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.
bits : 16 - 20 (5 bit)

RX_FIFO_EN : Receive FIFO enabled for SPI transactions.
bits : 22 - 22 (1 bit)

Enumeration:

0 : DIS

Receive FIFO is not enabled.

1 : en

Receive FIFO is enabled.

End of enumeration elements list.

RX_FIFO_CLEAR : Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
bits : 23 - 23 (1 bit)

Enumeration:

1 : CLEAR

Clear the Receive FIFO, clears any pending RX FIFO status.

End of enumeration elements list.

RX_FIFO_CNT : Count of entries in RX FIFO.
bits : 24 - 29 (6 bit)
access : read-only

RX_DMA_EN : RX DMA Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : dis

RX DMA requests are disabled, any pending DMA requests are cleared.

1 : en

RX DMA requests are enabled.

End of enumeration elements list.


DATA16[1]

Register for reading and writing the FIFO.
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA16[1] DATA16[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 15 (16 bit)


DATA161

Register for reading and writing the FIFO.
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA161 DATA161 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 15 (16 bit)


DATA82

Register for reading and writing the FIFO.
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA82 DATA82 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)


INT_FL

Register for reading and clearing interrupt flags. All bits are write 1 to clear.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_FL INT_FL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_THRESH TX_EMPTY RX_THRESH RX_FULL SSA SSD FAULT ABORT M_DONE TX_OVR TX_UND RX_OVR RX_UND

TX_THRESH : TX FIFO Threshold Crossed.
bits : 0 - 0 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

TX_EMPTY : TX FIFO Empty.
bits : 1 - 1 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

RX_THRESH : RX FIFO Threshold Crossed.
bits : 2 - 2 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

RX_FULL : RX FIFO FULL.
bits : 3 - 3 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

SSA : Slave Select Asserted.
bits : 4 - 4 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

SSD : Slave Select Deasserted.
bits : 5 - 5 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

FAULT : Multi-Master Mode Fault.
bits : 8 - 8 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

ABORT : Slave Abort Detected.
bits : 9 - 9 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

M_DONE : Master Done, set when SPI Master has completed any transactions.
bits : 11 - 11 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

TX_OVR : Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.
bits : 12 - 12 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

TX_UND : Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.
bits : 13 - 13 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

RX_OVR : Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.
bits : 14 - 14 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

RX_UND : Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.
bits : 15 - 15 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.


INT_EN

Register for enabling interrupts.
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_EN INT_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_THRESH TX_EMPTY RX_THRESH RX_FULL SSA SSD FAULT ABORT M_DONE TX_OVR TX_UND RX_OVR RX_UND

TX_THRESH : TX FIFO Threshold interrupt enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

TX_EMPTY : TX FIFO Empty interrupt enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

RX_THRESH : RX FIFO Threshold Crossed interrupt enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

RX_FULL : RX FIFO FULL interrupt enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

SSA : Slave Select Asserted interrupt enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

SSD : Slave Select Deasserted interrupt enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

FAULT : Multi-Master Mode Fault interrupt enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

ABORT : Slave Abort Detected interrupt enable.
bits : 9 - 9 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

M_DONE : Master Done interrupt enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

TX_OVR : Transmit FIFO Overrun interrupt enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

TX_UND : Transmit FIFO Underrun interrupt enable.
bits : 13 - 13 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

RX_OVR : Receive FIFO Overrun interrupt enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.

RX_UND : Receive FIFO Underrun interrupt enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : dis

Interrupt is disabled.

1 : en

Interrupt is enabled.

End of enumeration elements list.


WAKE_FL

Register for wake up flags. All bits in this register are write 1 to clear.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKE_FL WAKE_FL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_THRESH TX_EMPTY RX_THRESH RX_FULL

TX_THRESH : Wake on TX FIFO Threshold Crossed.
bits : 0 - 0 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

TX_EMPTY : Wake on TX FIFO Empty.
bits : 1 - 1 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

RX_THRESH : Wake on RX FIFO Threshold Crossed.
bits : 2 - 2 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.

RX_FULL : Wake on RX FIFO Full.
bits : 3 - 3 (1 bit)

Enumeration:

1 : clear

Flag is set when value read is 1. Write 1 to clear this flag.

End of enumeration elements list.


WAKE_EN

Register for wake up enable.
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKE_EN WAKE_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_THRESH TX_EMPTY RX_THRESH RX_FULL

TX_THRESH : Wake on TX FIFO Threshold Crossed Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

Wakeup source disabled.

1 : en

Wakeup source enabled.

End of enumeration elements list.

TX_EMPTY : Wake on TX FIFO Empty Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : dis

Wakeup source disabled.

1 : en

Wakeup source enabled.

End of enumeration elements list.

RX_THRESH : Wake on RX FIFO Threshold Crossed Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : dis

Wakeup source disabled.

1 : en

Wakeup source enabled.

End of enumeration elements list.

RX_FULL : Wake on RX FIFO Full Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : dis

Wakeup source disabled.

1 : en

Wakeup source enabled.

End of enumeration elements list.


DATA8[2]

Register for reading and writing the FIFO.
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA8[2] DATA8[2] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)


DATA83

Register for reading and writing the FIFO.
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA83 DATA83 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)


STAT

SPI Status register.
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY

BUSY : SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.
bits : 0 - 0 (1 bit)

Enumeration:

0 : not

SPI not active.

1 : active

SPI active.

End of enumeration elements list.


CTRL0

Register for controlling SPI peripheral.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0 CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN MASTER SS_IO START SS_CTRL SS

EN : SPI Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

SPI is disabled.

1 : en

SPI is enabled.

End of enumeration elements list.

MASTER : Master Mode Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : dis

SPI is Slave mode.

1 : en

SPI is Master mode.

End of enumeration elements list.

SS_IO : Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.
bits : 4 - 4 (1 bit)

Enumeration:

0 : output

Slave select 0 is output.

1 : input

Slave Select 0 is input, only valid if MMEN=1.

End of enumeration elements list.

START : Start Transmit.
bits : 5 - 5 (1 bit)

Enumeration:

1 : start

Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.

End of enumeration elements list.

SS_CTRL : Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.
bits : 8 - 8 (1 bit)

Enumeration:

0 : DEASSERT

SPI De-asserts Slave Select at the end of a transaction.

1 : ASSERT

SPI leaves Slave Select asserted at the end of a transaction.

End of enumeration elements list.

SS : Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.
bits : 16 - 19 (4 bit)

Enumeration:

0x1 : SS0

SS0 is selected.

0x2 : SS1

SS1 is selected.

0x4 : SS2

SS2 is selected.

0x8 : SS3

SS3 is selected.

End of enumeration elements list.


DATA8[3]

Register for reading and writing the FIFO.
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0

DATA8[3] DATA8[3] read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DATA

DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)


CTRL1

Register for controlling SPI peripheral.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_NUM_CHAR RX_NUM_CHAR

TX_NUM_CHAR : Nubmer of Characters to transmit.
bits : 0 - 15 (16 bit)

RX_NUM_CHAR : Nubmer of Characters to receive.
bits : 16 - 31 (16 bit)


CTRL2

Register for controlling SPI peripheral.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL SCLK_INV NUMBITS DATA_WIDTH THREE_WIRE SS_POL SRPOL

CPHA : Clock Phase.
bits : 0 - 0 (1 bit)

Enumeration:

0 : Rising_Edge

Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2

1 : Falling_Edge

Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3

End of enumeration elements list.

CPOL : Clock Polarity.
bits : 1 - 1 (1 bit)

Enumeration:

0 : Normal

Normal Clock. Use when in SPI Mode 0 and Mode 1

1 : Inverted

Inverted Clock. Use when in SPI Mode 2 and Mode 3

End of enumeration elements list.

SCLK_INV : Reserved - Must Always Be Cleared to 0.
bits : 4 - 4 (1 bit)

NUMBITS : Number of Bits per character.
bits : 8 - 11 (4 bit)

Enumeration:

0 : 0

16 bits per character.

End of enumeration elements list.

DATA_WIDTH : SPI Data width.
bits : 12 - 13 (2 bit)

Enumeration:

0 : Mono

1 data pin.

1 : Dual

2 data pins.

2 : Quad

4 data pins.

End of enumeration elements list.

THREE_WIRE : Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.
bits : 15 - 15 (1 bit)

Enumeration:

0 : dis

Use four wire mode (Mono only).

1 : en

Use three wire mode.

End of enumeration elements list.

SS_POL : Slave Select Polarity, each Slave Select can have unique polarity.
bits : 16 - 23 (8 bit)

Enumeration:

0x1 : SS0_high

SS0 active high.

0x2 : SS1_high

SS1 active high.

0x4 : SS2_high

SS2 active high.

0x8 : SS3_high

SS3 active high.

End of enumeration elements list.

SRPOL : Slave Ready Polarity, each Slave Ready can have unique polarity.
bits : 24 - 31 (8 bit)

Enumeration:

0x1 : SR0_high

SR0 active high.

0x2 : SR1_high

SR1 active high.

0x4 : SR2_high

SR2 active high.

0x8 : SR3_high

SR3 active high.

0x10 : SR4_high

SR4 active high.

0x20 : SR5_high

SR5 active high.

0x40 : SR6_high

SR6 active high.

0x80 : SR7_high

SR7 active high.

End of enumeration elements list.



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