Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SPI 16-bit Data Access
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SPI data.
bits : 0 - 15 (16 bit)
SPI Data 8-bit access
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA16
reset_Mask : 0x0
DATA : SPI data.
bits : 0 - 7 (8 bit)
SPI 16-bit Data Access
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SPI data.
bits : 0 - 15 (16 bit)
SPI Data 8-bit access
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA16
reset_Mask : 0x0
DATA : SPI data.
bits : 0 - 7 (8 bit)
SPI Data 8-bit access
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA16
reset_Mask : 0x0
DATA : SPI data.
bits : 0 - 7 (8 bit)
SPI Data 8-bit access
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA16
reset_Mask : 0x0
DATA : SPI data.
bits : 0 - 7 (8 bit)
Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4).
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BRG : Baud Rate Reload Value.
bits : 0 - 15 (16 bit)
Baud Rate Reload Value. The SPI Baud Rate register is a 16-bit reload value for the SPI Baud Rate Generator. The reload value must be greater than or equal to 0002H for proper SPI operation (maximum baud rate is PCLK frequency divided by 4).
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BRG : Baud Rate Reload Value.
bits : 0 - 15 (16 bit)
SPI DMA Register.
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_FIFO_LEVEL : Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.
bits : 0 - 2 (3 bit)
Enumeration: fifo_level_enum
0 : entry1
None
1 : entries2
None
2 : entries3
None
3 : entries4
None
4 : entries5
None
5 : entries6
None
6 : entries7
None
7 : entries8
None
End of enumeration elements list.
TX_FIFO_CLEAR : Transmit FIFO Clear.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration: start_op_enum
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
TX_FIFO_CNT : Transmit FIFO Count.
bits : 8 - 11 (4 bit)
access : read-only
TX_DMA_EN : Transmit DMA Enable.
bits : 15 - 15 (1 bit)
Enumeration: dis_en_enum
0 : disable
None
1 : enable
None
End of enumeration elements list.
RX_FIFO_LEVEL : Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.
bits : 16 - 18 (3 bit)
Enumeration: fifo_level_enum
0 : entry1
None
1 : entries2
None
2 : entries3
None
3 : entries4
None
4 : entries5
None
5 : entries6
None
6 : entries7
None
7 : entries8
None
End of enumeration elements list.
RX_FIFO_CLEAR : Receive FIFO Clear.
bits : 20 - 20 (1 bit)
Enumeration: start_op_enum
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
RX_FIFO_CNT : Receive FIFO Count.
bits : 24 - 27 (4 bit)
access : read-only
RX_DMA_EN : Receive DMA Enable.
bits : 31 - 31 (1 bit)
Enumeration: dis_en_enum
0 : disable
None
1 : enable
None
End of enumeration elements list.
SPI DMA Register.
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_FIFO_LEVEL : Transmit FIFO Level. Set the number of free entries in the TxFIFO when a TxDMA request occurs.
bits : 0 - 2 (3 bit)
Enumeration: fifo_level_enum
0 : entry1
1 : entries2
2 : entries3
3 : entries4
4 : entries5
5 : entries6
6 : entries7
7 : entries8
End of enumeration elements list.
TX_FIFO_CLEAR : Transmit FIFO Clear.
bits : 4 - 4 (1 bit)
access : write-only
Enumeration: start_op_enum
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
TX_FIFO_CNT : Transmit FIFO Count.
bits : 8 - 11 (4 bit)
access : read-only
TX_DMA_EN : Transmit DMA Enable.
bits : 15 - 15 (1 bit)
Enumeration: dis_en_enum
0 : disable
1 : enable
End of enumeration elements list.
RX_FIFO_LEVEL : Receive FIFO Level. Sets the RX FIFO DMA request threshold. This configures the number of filled RxFIFO entries before activating an RxDMA request.
bits : 16 - 18 (3 bit)
Enumeration: fifo_level_enum
0 : entry1
1 : entries2
2 : entries3
3 : entries4
4 : entries5
5 : entries6
6 : entries7
7 : entries8
End of enumeration elements list.
RX_FIFO_CLEAR : Receive FIFO Clear.
bits : 20 - 20 (1 bit)
Enumeration: start_op_enum
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
RX_FIFO_CNT : Receive FIFO Count.
bits : 24 - 27 (4 bit)
access : read-only
RX_DMA_EN : Receive DMA Enable.
bits : 31 - 31 (1 bit)
Enumeration: dis_en_enum
0 : disable
1 : enable
End of enumeration elements list.
I2S Control Register.
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
I2S_EN : I2S Mode Enable.
bits : 0 - 0 (1 bit)
Enumeration: dis_en_enum
0 : disable
None
1 : enable
None
End of enumeration elements list.
I2S_MUTE : I2S Mute transmit.
bits : 1 - 1 (1 bit)
Enumeration:
0 : normal
Normal Transmit.
1 : replaced
Transmit data is replaced with 0.
End of enumeration elements list.
I2S_PAUSE : I2S Pause transmit/receive.
bits : 2 - 2 (1 bit)
Enumeration:
0 : normal
Normal Transmit.
1 : halt
Halt transmit and receive FIFO and DMA access, transmit 0's.
End of enumeration elements list.
I2S_MONO : I2S Monophonic Audio Mode.
bits : 3 - 3 (1 bit)
Enumeration:
0 : stereophonic
Stereophonic audio.
1 : monophonic
Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
End of enumeration elements list.
I2S_LJ : I2S Left Justify.
bits : 4 - 4 (1 bit)
Enumeration:
0 : normal
Normal I2S audio protocol.
1 : replaced
Audio data is synchronized with SSEL.
End of enumeration elements list.
I2S Control Register.
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
I2S_EN : I2S Mode Enable.
bits : 0 - 0 (1 bit)
Enumeration: dis_en_enum
0 : disable
1 : enable
End of enumeration elements list.
I2S_MUTE : I2S Mute transmit.
bits : 1 - 1 (1 bit)
Enumeration:
0 : normal
Normal Transmit.
1 : replaced
Transmit data is replaced with 0.
End of enumeration elements list.
I2S_PAUSE : I2S Pause transmit/receive.
bits : 2 - 2 (1 bit)
Enumeration:
0 : normal
Normal Transmit.
1 : halt
Halt transmit and receive FIFO and DMA access, transmit 0's.
End of enumeration elements list.
I2S_MONO : I2S Monophonic Audio Mode.
bits : 3 - 3 (1 bit)
Enumeration:
0 : stereophonic
Stereophonic audio.
1 : monophonic
Monophonic audio format.Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
End of enumeration elements list.
I2S_LJ : I2S Left Justify.
bits : 4 - 4 (1 bit)
Enumeration:
0 : normal
Normal I2S audio protocol.
1 : replaced
Audio data is synchronized with SSEL.
End of enumeration elements list.
SPI Control Register.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Enable.
bits : 0 - 0 (1 bit)
Enumeration: dis_en_enum
0 : disable
None
1 : enable
None
End of enumeration elements list.
MMEN : SPI Master Mode Enable.
bits : 1 - 1 (1 bit)
Enumeration: slv_mst_enum
0 : slave
None
1 : master
None
End of enumeration elements list.
WOR : Wired OR (open drain) Enable.
bits : 2 - 2 (1 bit)
Enumeration: dis_en_enum
0 : disable
None
1 : enable
None
End of enumeration elements list.
CLKPOL : Clock Polarity.
bits : 3 - 3 (1 bit)
Enumeration: spi_pol_enum
0 : idleLo
SCLK idles Low (0) after character transmission/reception.
1 : idleHi
SCLK idles High (1) after character transmission/reception.
End of enumeration elements list.
PHASE : Phase Select.
bits : 4 - 4 (1 bit)
Enumeration: spi_phase_enum
0 : activeEdge
Transmit on active edge of SCLK.
1 : inactiveEdge
Transmit on inactive edge of SCLK.
End of enumeration elements list.
BIRQ : Baud Rate Generator Timer Interrupt Request.
bits : 5 - 5 (1 bit)
Enumeration: dis_en_enum
0 : disable
None
1 : enable
None
End of enumeration elements list.
STR : Start SPI Interrupt.
bits : 6 - 6 (1 bit)
Enumeration: start_op_enum
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
IRQE : Interrupt Request Enable.
bits : 7 - 7 (1 bit)
Enumeration: dis_en_enum
0 : disable
None
1 : enable
None
End of enumeration elements list.
SPI Control Register.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Enable.
bits : 0 - 0 (1 bit)
Enumeration: dis_en_enum
0 : disable
1 : enable
End of enumeration elements list.
MMEN : SPI Master Mode Enable.
bits : 1 - 1 (1 bit)
Enumeration: slv_mst_enum
0 : slave
1 : master
End of enumeration elements list.
WOR : Wired OR (open drain) Enable.
bits : 2 - 2 (1 bit)
Enumeration: dis_en_enum
0 : disable
1 : enable
End of enumeration elements list.
CLKPOL : Clock Polarity.
bits : 3 - 3 (1 bit)
Enumeration: spi_pol_enum
0 : idleLo
SCLK idles Low (0) after character transmission/reception.
1 : idleHi
SCLK idles High (1) after character transmission/reception.
End of enumeration elements list.
PHASE : Phase Select.
bits : 4 - 4 (1 bit)
Enumeration: spi_phase_enum
0 : activeEdge
Transmit on active edge of SCLK.
1 : inactiveEdge
Transmit on inactive edge of SCLK.
End of enumeration elements list.
BIRQ : Baud Rate Generator Timer Interrupt Request.
bits : 5 - 5 (1 bit)
Enumeration: dis_en_enum
0 : disable
1 : enable
End of enumeration elements list.
STR : Start SPI Interrupt.
bits : 6 - 6 (1 bit)
Enumeration: start_op_enum
0 : complete
No operation/complete.
1 : start
Start operation.
End of enumeration elements list.
IRQE : Interrupt Request Enable.
bits : 7 - 7 (1 bit)
Enumeration: dis_en_enum
0 : disable
1 : enable
End of enumeration elements list.
SPI Status Register.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLAS : Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration: sel_enum
0 : selected
None
1 : notSelected
None
End of enumeration elements list.
TXST : Transmit Status.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration: busy_enum
0 : idle
None
1 : busy
None
End of enumeration elements list.
TUND : Transmit Underrun.
bits : 2 - 2 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
ROVR : Receive Overrun.
bits : 3 - 3 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
ABT : Slave Mode Transaction Abort.
bits : 4 - 4 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
COL : Collision.
bits : 5 - 5 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
TOVR : Transmit Overrun.
bits : 6 - 6 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
IRQ : SPI Interrupt Request.
bits : 7 - 7 (1 bit)
Enumeration: flag_enum
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
SPI Status Register.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SLAS : Slave Select. If the SPI is in slave mode, this bit indicates if the SPI is selected. If the SPI is in master mode this bit has no meaning.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration: sel_enum
0 : selected
1 : notSelected
End of enumeration elements list.
TXST : Transmit Status.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration: busy_enum
0 : idle
1 : busy
End of enumeration elements list.
TUND : Transmit Underrun.
bits : 2 - 2 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
ROVR : Receive Overrun.
bits : 3 - 3 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
ABT : Slave Mode Transaction Abort.
bits : 4 - 4 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
COL : Collision.
bits : 5 - 5 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
TOVR : Transmit Overrun.
bits : 6 - 6 (1 bit)
Enumeration: event_flag_enum
0 : noEvent
The event has not occurred.
1 : occurred
The event has occurred.
End of enumeration elements list.
IRQ : SPI Interrupt Request.
bits : 7 - 7 (1 bit)
Enumeration: flag_enum
0 : inactive
No interrupt is pending.
1 : pending
An interrupt is pending.
End of enumeration elements list.
SPI Mode Register.
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SSV : Slave Select Value.
bits : 0 - 0 (1 bit)
Enumeration: lo_hi_enum
0 : lo
The SSEL pin will be driven low.
1 : hi
The SSEL pin will be driven high.
End of enumeration elements list.
SSIO : Slave Select I/O.
bits : 1 - 1 (1 bit)
Enumeration: input_output_enum
0 : input
None
1 : output
None
End of enumeration elements list.
NUMBITS :
bits : 2 - 5 (4 bit)
Enumeration: spi_bits_enum
0 : bits16
None
1 : bits1
None
2 : bits2
None
3 : bits3
None
4 : bits4
None
5 : bits5
None
6 : bits6
None
7 : bits7
None
8 : bits8
None
9 : bits9
None
10 : bits10
None
11 : bits11
None
12 : bits12
None
13 : bits13
None
14 : bits14
None
15 : bits15
None
End of enumeration elements list.
TX_LJ : Transmit Left Justify.
bits : 7 - 7 (1 bit)
Enumeration: dis_en_enum
0 : disable
None
1 : enable
None
End of enumeration elements list.
SSL1 : Slave Select 1. If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit.
bits : 8 - 8 (1 bit)
Enumeration: hi_lo_enum
0 : hi
High.
1 : lo
Low.
End of enumeration elements list.
SSL2 : Slave Select 2. If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit.
bits : 9 - 9 (1 bit)
Enumeration: hi_lo_enum
0 : hi
High.
1 : lo
Low.
End of enumeration elements list.
SSL3 : Slave Select 3. If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit.
bits : 10 - 10 (1 bit)
Enumeration: hi_lo_enum
0 : hi
High.
1 : lo
Low.
End of enumeration elements list.
SPI Mode Register.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SSV : Slave Select Value.
bits : 0 - 0 (1 bit)
Enumeration: lo_hi_enum
0 : lo
The SSEL pin will be driven low.
1 : hi
The SSEL pin will be driven high.
End of enumeration elements list.
SSIO : Slave Select I/O.
bits : 1 - 1 (1 bit)
Enumeration: input_output_enum
0 : input
1 : output
End of enumeration elements list.
NUMBITS :
bits : 2 - 5 (4 bit)
Enumeration: spi_bits_enum
0 : bits16
1 : bits1
2 : bits2
3 : bits3
4 : bits4
5 : bits5
6 : bits6
7 : bits7
8 : bits8
9 : bits9
10 : bits10
11 : bits11
12 : bits12
13 : bits13
14 : bits14
15 : bits15
End of enumeration elements list.
TX_LJ : Transmit Left Justify.
bits : 7 - 7 (1 bit)
Enumeration: dis_en_enum
0 : disable
1 : enable
End of enumeration elements list.
SSL1 : Slave Select 1. If SPI is enabled and in master mode, the SSEL_1 is driven according to this bit.
bits : 8 - 8 (1 bit)
Enumeration: hi_lo_enum
0 : hi
High.
1 : lo
Low.
End of enumeration elements list.
SSL2 : Slave Select 2. If SPI is enabled and in master mode, the SSEL_2 is driven according to this bit.
bits : 9 - 9 (1 bit)
Enumeration: hi_lo_enum
0 : hi
High.
1 : lo
Low.
End of enumeration elements list.
SSL3 : Slave Select 3. If SPI is enabled and in master mode, the SSEL_3 is driven according to this bit.
bits : 10 - 10 (1 bit)
Enumeration: hi_lo_enum
0 : hi
High.
1 : lo
Low.
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.