Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Count. This register stores the current timer count.
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Timer Control Register.
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMODE : Timer Mode.
bits : 0 - 2 (3 bit)
Enumeration:
0 : oneShot
One Shot Mode.
1 : continuous
Continuous Mode.
2 : counter
Counter Mode.
3 : pwm
PWM Mode.
4 : capture
Capture Mode.
5 : compare
Compare Mode.
6 : gated
Gated Mode.
7 : captureCompare
Capture/Compare Mode.
End of enumeration elements list.
PRES : Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0].
bits : 3 - 5 (3 bit)
Enumeration:
0 : div1
Divide by 1.
1 : div2
Divide by 2.
2 : div4
Divide by 4.
3 : div8
Divide by 8.
4 : div16
Divide by 16.
5 : div32
Divide by 32.
6 : div64
Divide by 64.
7 : div128
Divide by 128.
End of enumeration elements list.
TPOL : Timer input/output polarity bit.
bits : 6 - 6 (1 bit)
Enumeration:
0 : activeHi
Active High.
1 : activeLo
Active Low.
End of enumeration elements list.
TEN : Timer Enable.
bits : 7 - 7 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PRES3 : MSB of prescaler value.
bits : 8 - 8 (1 bit)
PWMSYNC : Timer PWM Synchronization Mode Enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
NOLHPOL : Timer PWM output 0A polarity bit.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
NOLLPOL : Timer PWM output 0A' polarity bit.
bits : 11 - 11 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
PWMCKBD : Timer PWM output 0A Mode Disable.
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disable.
0 : en
Enable.
End of enumeration elements list.
Timer Non-Overlapping Compare Register.
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NOLLCMP : Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'.
bits : 0 - 7 (8 bit)
NOLHCMP : Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A.
bits : 8 - 15 (8 bit)
Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWM. This register stores the value that is compared to the current timer count.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt.
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IRQ_CLR : Clear Interrupt.
bits : 0 - 0 (1 bit)
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