CN

DATA

RNG_IE : Random Number Interrupt Enable. This bit enables an interrupt to be generated when a new, 128 bit, random number is ready to be read.
bits : 2 - 2 (1 bit)

Enumeration:

End of enumeration elements list.

RNG_ISC : Random Number Interrupt Status Clear. Setting this bit to 1 clears the RNG_I4S bit and acknowledges the interrupt, if enabled. This bit is a write only bit and always reads as zero.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration: ( write )

End of enumeration elements list.

RNG_I4S : Random Number 4 Word Status. This bit is set when a new 128 bit random number is ready to be read (using 4 consecutive reads of the TRNG Data Register). When set, an interrupt will be generated if the RNG_IE bit is also set. This bit is cleared by setting the RNG_ISC bit.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RNG_IS : Random Number Word Status. This bit is set when at least one 32 bit random number is ready to be read. This bit is cleared by hardware if all the random words have been read. It is needed to poll this bit before reading the TRNG Data Register.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

AESKG : AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.
bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

DATA : Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.
bits : 0 - 31 (32 bit)