\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Control Register.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENABLE : UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
UART disabled. FIFOs are flushed. Clock is gated off for power savings.
1 : en
UART enabled.
End of enumeration elements list.
PARITY_EN : Enable/disable Parity bit (9th character).
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
No Parity
1 : en
Parity enabled as 9th bit
End of enumeration elements list.
PARITY : When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1 Space parity = always 0.
bits : 2 - 3 (2 bit)
Enumeration:
0 : Even
Even parity selected.
1 : ODD
Odd parity selected.
2 : MARK
Mark parity selected.
3 : SPACE
Space parity selected.
End of enumeration elements list.
PARMD : Selects parity based on 1s or 0s count (when PARITY_EN=1).
bits : 4 - 4 (1 bit)
Enumeration:
0 : 1
Parity calculation is based on number of 1s in frame.
1 : 0
Parity calculation is based on number of 0s in frame.
End of enumeration elements list.
TX_FLUSH : Flushes the TX FIFO buffer.
bits : 5 - 5 (1 bit)
RX_FLUSH : Flushes the RX FIFO buffer.
bits : 6 - 6 (1 bit)
BITACC : If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.
bits : 7 - 7 (1 bit)
Enumeration:
0 : FRAME
Frame accuracy.
1 : BIT
Bit accuracy.
End of enumeration elements list.
CHAR_SIZE : Selects UART character size.
bits : 8 - 9 (2 bit)
Enumeration:
0 : 5
5 bits.
1 : 6
6 bits.
2 : 7
7 bits.
3 : 8
8 bits.
End of enumeration elements list.
STOPBITS : Selects the number of stop bits that will be generated.
bits : 10 - 10 (1 bit)
Enumeration:
0 : 1
1 stop bit.
1 : 1_5
1.5 stop bits.
End of enumeration elements list.
FLOW_CTRL : Enables/disables hardware flow control.
bits : 11 - 11 (1 bit)
Enumeration:
1 : en
HW Flow Control with RTS/CTS enabled
0 : dis
HW Flow Control disabled
End of enumeration elements list.
FLOW_POL : RTS/CTS polarity.
bits : 12 - 12 (1 bit)
Enumeration:
0 : 0
RTS/CTS asserted is logic 0.
1 : 1
RTS/CTS asserted is logic 1.
End of enumeration elements list.
NULL_MODEM : NULL Modem Support (RTS/CTS and TXD/RXD swap).
bits : 13 - 13 (1 bit)
Enumeration:
0 : DIS
Direct convention.
1 : EN
Null Modem Mode.
End of enumeration elements list.
BREAK : Break control bit. It causes a break condition to be transmitted to receiving UART.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DIS
Break characters are not generated.
1 : EN
Break characters are sent(all the bits are at '0' including start/parity/stop).
End of enumeration elements list.
CLKSEL : Baud Rate Clock Source Select. Selects the baud rate clock.
bits : 15 - 15 (1 bit)
Enumeration:
0 : SYSTEM
System clock.
1 : ALTERNATE
Alternate 7.3727MHz internal clock. Useful in low power modes when the system clock is slow.
End of enumeration elements list.
RX_TO : RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read.
bits : 16 - 23 (8 bit)
Interrupt Status Flags.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_FRAME_ERROR : FLAG for RX Frame Error Interrupt.
bits : 0 - 0 (1 bit)
RX_PARITY_ERROR : FLAG for RX Parity Error interrupt.
bits : 1 - 1 (1 bit)
CTS_CHANGE : FLAG for CTS signal change interrupt.
bits : 2 - 2 (1 bit)
RX_OVERRUN : FLAG for RX FIFO Overrun interrupt.
bits : 3 - 3 (1 bit)
RX_FIFO_THRESH : FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
bits : 4 - 4 (1 bit)
TX_FIFO_ALMOST_EMPTY : FLAG for interrupt when TX FIFO has only one byte remaining.
bits : 5 - 5 (1 bit)
TX_FIFO_THRESH : FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
bits : 6 - 6 (1 bit)
BREAK : FLAG for received BREAK character interrupt.
bits : 7 - 7 (1 bit)
RX_TIMEOUT : FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
bits : 8 - 8 (1 bit)
LAST_BREAK : FLAG for Last break character interrupt.
bits : 9 - 9 (1 bit)
Baud rate register. Integer portion.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IBAUD : Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).
bits : 0 - 11 (12 bit)
FACTOR : FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.
bits : 16 - 17 (2 bit)
Enumeration:
0 : 128
Baud Factor 128
1 : 64
Baud Factor 64
2 : 32
Baud Factor 32
3 : 16
Baud Factor 16
End of enumeration elements list.
Baud rate register. Decimal Setting.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DBAUD : Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.
bits : 0 - 11 (12 bit)
FIFO Data buffer.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FIFO : Load/unload location for TX and RX FIFO buffers.
bits : 0 - 7 (8 bit)
DMA Configuration.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TDMA_EN : TX DMA channel enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
DMA is disabled
1 : en
DMA is enabled
End of enumeration elements list.
RXDMA_EN : RX DMA channel enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
DMA is disabled
1 : en
DMA is enabled
End of enumeration elements list.
TXDMA_LEVEL : TX threshold for DMA transmission.
bits : 8 - 13 (6 bit)
RXDMA_LEVEL : RX threshold for DMA transmission.
bits : 16 - 21 (6 bit)
Transmit FIFO Status register.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned).
bits : 0 - 6 (7 bit)
Threshold Control register.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO_THRESH : RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.
bits : 0 - 5 (6 bit)
TX_FIFO_THRESH : TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.
bits : 8 - 13 (6 bit)
RTS_FIFO_THRESH : RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.
bits : 16 - 21 (6 bit)
Status Register.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TX_BUSY : Read-only flag indicating the UART transmit status.
bits : 0 - 0 (1 bit)
access : read-only
RX_BUSY : Read-only flag indicating the UARTreceiver status.
bits : 1 - 1 (1 bit)
access : read-only
PARITY : 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.
bits : 2 - 2 (1 bit)
access : read-only
BREAK : Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
bits : 3 - 3 (1 bit)
access : read-only
RX_EMPTY : Read-only flag indicating the RX FIFO state.
bits : 4 - 4 (1 bit)
access : read-only
RX_FULL : Read-only flag indicating the RX FIFO state.
bits : 5 - 5 (1 bit)
access : read-only
TX_EMPTY : Read-only flag indicating the TX FIFO state.
bits : 6 - 6 (1 bit)
access : read-only
TX_FULL : Read-only flag indicating the TX FIFO state.
bits : 7 - 7 (1 bit)
access : read-only
RX_FIFO_CNT : Indicates the number of bytes currently in the RX FIFO.
bits : 8 - 13 (6 bit)
access : read-only
TX_FIFO_CNT : Indicates the number of bytes currently in the TX FIFO.
bits : 16 - 21 (6 bit)
access : read-only
RX_TO : RX Timeout status.
bits : 24 - 24 (1 bit)
access : read-only
Interrupt Enable Register.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX_FRAME_ERROR : Enable for RX Frame Error Interrupt.
bits : 0 - 0 (1 bit)
RX_PARITY_ERROR : Enable for RX Parity Error interrupt.
bits : 1 - 1 (1 bit)
CTS_CHANGE : Enable for CTS signal change interrupt.
bits : 2 - 2 (1 bit)
RX_OVERRUN : Enable for RX FIFO OVerrun interrupt.
bits : 3 - 3 (1 bit)
RX_FIFO_THRESH : Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
bits : 4 - 4 (1 bit)
TX_FIFO_ALMOST_EMPTY : Enable for interrupt when TX FIFO has only one byte remaining.
bits : 5 - 5 (1 bit)
TX_FIFO_THRESH : Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
bits : 6 - 6 (1 bit)
BREAK : Enable for received BREAK character interrupt.
bits : 7 - 7 (1 bit)
RX_TIMEOUT : Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
bits : 8 - 8 (1 bit)
LAST_BREAK : Enable for Last break character interrupt.
bits : 9 - 9 (1 bit)
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