CTRL

INT_FL

BAUD0

BAUD1

FIFO

DMA

TX_FIFO

THRESH_CTRL

STATUS

INT_EN

ENABLE : UART enabled, to enable UART block, it is used to drive a gated clock in order to save power consumption when UART is not used. FIFOs are flushed when UART is disabled.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

PARITY_EN : Enable/disable Parity bit (9th character).
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

PARITY : When PARITY_EN=1, selects odd, even, Mark or Space parity. Mark parity = always 1 Space parity = always 0.
bits : 2 - 3 (2 bit)

Enumeration:

End of enumeration elements list.

PARMD : Selects parity based on 1s or 0s count (when PARITY_EN=1).
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

TX_FLUSH : Flushes the TX FIFO buffer.
bits : 5 - 5 (1 bit)

RX_FLUSH : Flushes the RX FIFO buffer.
bits : 6 - 6 (1 bit)

BITACC : If set, bit accuracy is selected, in this case the bit duration is the same for all the bits with the optimal accuracy. But the frame duration can have a significant deviation from the expected baudrate.If clear, frame accuracy is selected, therefore bits can have different duration in order to guarantee the minimum frame deviation.
bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

CHAR_SIZE : Selects UART character size.
bits : 8 - 9 (2 bit)

Enumeration:

End of enumeration elements list.

STOPBITS : Selects the number of stop bits that will be generated.
bits : 10 - 10 (1 bit)

Enumeration:

End of enumeration elements list.

FLOW_CTRL : Enables/disables hardware flow control.
bits : 11 - 11 (1 bit)

Enumeration:

End of enumeration elements list.

FLOW_POL : RTS/CTS polarity.
bits : 12 - 12 (1 bit)

Enumeration:

End of enumeration elements list.

NULL_MODEM : NULL Modem Support (RTS/CTS and TXD/RXD swap).
bits : 13 - 13 (1 bit)

Enumeration:

End of enumeration elements list.

BREAK : Break control bit. It causes a break condition to be transmitted to receiving UART.
bits : 14 - 14 (1 bit)

Enumeration:

End of enumeration elements list.

CLKSEL : Baud Rate Clock Source Select. Selects the baud rate clock.
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

RX_TO : RX Time Out. RX time out interrupt will occur after RXTO Uart characters if RX-FIFO is not empty and RX FIFO has not been read.
bits : 16 - 23 (8 bit)

RX_FRAME_ERROR : FLAG for RX Frame Error Interrupt.
bits : 0 - 0 (1 bit)

RX_PARITY_ERROR : FLAG for RX Parity Error interrupt.
bits : 1 - 1 (1 bit)

CTS_CHANGE : FLAG for CTS signal change interrupt.
bits : 2 - 2 (1 bit)

RX_OVERRUN : FLAG for RX FIFO Overrun interrupt.
bits : 3 - 3 (1 bit)

RX_FIFO_THRESH : FLAG for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
bits : 4 - 4 (1 bit)

TX_FIFO_ALMOST_EMPTY : FLAG for interrupt when TX FIFO has only one byte remaining.
bits : 5 - 5 (1 bit)

TX_FIFO_THRESH : FLAG for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
bits : 6 - 6 (1 bit)

BREAK : FLAG for received BREAK character interrupt.
bits : 7 - 7 (1 bit)

RX_TIMEOUT : FLAG for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
bits : 8 - 8 (1 bit)

LAST_BREAK : FLAG for Last break character interrupt.
bits : 9 - 9 (1 bit)

IBAUD : Integer portion of baud rate divisor value. IBAUD = InputClock / (factor * Baud Rate Frequency).
bits : 0 - 11 (12 bit)

FACTOR : FACTOR must be chosen to have IDIV>0. factor used in calculation = 128 >> FACTOR.
bits : 16 - 17 (2 bit)

Enumeration:

End of enumeration elements list.

DBAUD : Decimal portion of baud rate divisor value. DIV = InputClock/(factor*Baud Rate Frequency). DDIV=(DIV-IDIV)*128.
bits : 0 - 11 (12 bit)

FIFO : Load/unload location for TX and RX FIFO buffers.
bits : 0 - 7 (8 bit)

TDMA_EN : TX DMA channel enable.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

RXDMA_EN : RX DMA channel enable.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

TXDMA_LEVEL : TX threshold for DMA transmission.
bits : 8 - 13 (6 bit)

RXDMA_LEVEL : RX threshold for DMA transmission.
bits : 16 - 21 (6 bit)

DATA : Reading from this field returns the next character available at the output of the TX FIFO (if one is available, otherwise 00h is returned).
bits : 0 - 6 (7 bit)

RX_FIFO_THRESH : RX FIFO Threshold Level.When the RX FIFO reaches this many bytes or higher, UARTn_INFTL.rx_fifo_level is set.
bits : 0 - 5 (6 bit)

TX_FIFO_THRESH : TX FIFO Threshold Level. When the TX FIFO reaches this many bytes or higher, UARTn_INTFL.tx_fifo_level is set.
bits : 8 - 13 (6 bit)

RTS_FIFO_THRESH : RTS threshold control. When the RX FIFO reaches this many bytes or higher, the RTS output signal is deasserted, informing the transmitting UART to stop sending data to this UART.
bits : 16 - 21 (6 bit)

TX_BUSY : Read-only flag indicating the UART transmit status.
bits : 0 - 0 (1 bit)
access : read-only

RX_BUSY : Read-only flag indicating the UARTreceiver status.
bits : 1 - 1 (1 bit)
access : read-only

PARITY : 9th Received bit state. This bit identifies the state of the 9th bit of received data. Only available for UART_CTRL.SIZE[1:0]=3.
bits : 2 - 2 (1 bit)
access : read-only

BREAK : Received BREAK status. BREAKS is cleared when UART_STAT register is read. Received data input is held in spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + Parity + Stop bits).
bits : 3 - 3 (1 bit)
access : read-only

RX_EMPTY : Read-only flag indicating the RX FIFO state.
bits : 4 - 4 (1 bit)
access : read-only

RX_FULL : Read-only flag indicating the RX FIFO state.
bits : 5 - 5 (1 bit)
access : read-only

TX_EMPTY : Read-only flag indicating the TX FIFO state.
bits : 6 - 6 (1 bit)
access : read-only

TX_FULL : Read-only flag indicating the TX FIFO state.
bits : 7 - 7 (1 bit)
access : read-only

RX_FIFO_CNT : Indicates the number of bytes currently in the RX FIFO.
bits : 8 - 13 (6 bit)
access : read-only

TX_FIFO_CNT : Indicates the number of bytes currently in the TX FIFO.
bits : 16 - 21 (6 bit)
access : read-only

RX_TO : RX Timeout status.
bits : 24 - 24 (1 bit)
access : read-only

RX_FRAME_ERROR : Enable for RX Frame Error Interrupt.
bits : 0 - 0 (1 bit)

RX_PARITY_ERROR : Enable for RX Parity Error interrupt.
bits : 1 - 1 (1 bit)

CTS_CHANGE : Enable for CTS signal change interrupt.
bits : 2 - 2 (1 bit)

RX_OVERRUN : Enable for RX FIFO OVerrun interrupt.
bits : 3 - 3 (1 bit)

RX_FIFO_THRESH : Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.
bits : 4 - 4 (1 bit)

TX_FIFO_ALMOST_EMPTY : Enable for interrupt when TX FIFO has only one byte remaining.
bits : 5 - 5 (1 bit)

TX_FIFO_THRESH : Enable for interrupt when TX FIFO reaches the number of bytes configured by the TXTHD field.
bits : 6 - 6 (1 bit)

BREAK : Enable for received BREAK character interrupt.
bits : 7 - 7 (1 bit)

RX_TIMEOUT : Enable for RX Timeout Interrupt. Trigger if there is no RX communication during n UART characters (n=UART_CN.RXTO).
bits : 8 - 8 (1 bit)

LAST_BREAK : Enable for Last break character interrupt.
bits : 9 - 9 (1 bit)