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USBHS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

FADDR

POWER

INMAXP

CSR0

INCSRL

INCSRU

OUTMAXP

OUTCSRL

OUTCSRU

COUNT0

OUTCOUNT

INTRIN

FIFO0

FIFO1

FIFO2

FIFO3

FIFO4

FIFO5

FIFO6

FIFO7

INTROUT

FIFO8

M31_PHY_PONRST

M31_PHY_NONCRY_RSTB

M31_PHY_NONCRY_EN

M31_PHY_PLL_EN

M31_PHY_OSCOUTEN

FIFO9

M31_PHY_CORECLKIN

M31_PHY_XTLSEL

M31_PHY_OUTCLKSEL

FIFO10

MXM_INT

MXM_INT_EN

MXM_SUSPEND

MXM_REG_A4

FIFO11

FIFO12

FIFO13

FIFO14

FIFO15

INTRINEN

HWVERS

EPINFO

RAMINFO

SOFTRESET

EARLYDMA

INTROUTEN

CTUCH

CTHSRTN

INTRUSB

INTRUSBEN

FRAME

INDEX

TESTMODE


FADDR

Function address register.
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FADDR FADDR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ADDR UPDATE

ADDR : Function address for this controller.
bits : 0 - 6 (7 bit)
access : read-write

UPDATE : Set when ADDR is written, cleared when new address takes effect.
bits : 7 - 7 (1 bit)
access : read-only


POWER

Power management register.
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

POWER POWER read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EN_SUSPENDM SUSPEND RESUME RESET HS_MODE HS_ENABLE SOFTCONN ISO_UPDATE

EN_SUSPENDM : Enable SUSPENDM signal.
bits : 0 - 0 (1 bit)
access : read-write

SUSPEND : Suspend mode detected.
bits : 1 - 1 (1 bit)
access : read-only

RESUME : Generate resume signaling.
bits : 2 - 2 (1 bit)
access : read-write

RESET : Bus reset detected.
bits : 3 - 3 (1 bit)
access : read-only

HS_MODE : High-speed mode detected.
bits : 4 - 4 (1 bit)
access : read-only

HS_ENABLE : High-speed mode enable.
bits : 5 - 5 (1 bit)
access : read-write

SOFTCONN : Softconn.
bits : 6 - 6 (1 bit)
access : read-write

ISO_UPDATE : Wait for SOF during Isochronous xfers.
bits : 7 - 7 (1 bit)
access : read-write


INMAXP

Maximum packet size for INx endpoint (x == INDEX).
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INMAXP INMAXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXPACKETSIZE NUMPACKMINUS1

MAXPACKETSIZE : Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9
bits : 0 - 10 (11 bit)

NUMPACKMINUS1 : Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases.
bits : 11 - 15 (5 bit)


CSR0

Control status register for EP 0 (when INDEX == 0).
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CSR0 CSR0 read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OUTPKTRDY INPKTRDY SENT_STALL DATA_END SETUP_END SEND_STALL SERV_OUTPKTRDY SERV_SETUP_END

OUTPKTRDY : EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO.
bits : 0 - 0 (1 bit)
access : read-only

INPKTRDY : EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared.
bits : 1 - 1 (1 bit)
access : read-write

SENT_STALL : Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear.
bits : 2 - 2 (1 bit)
access : read-write

DATA_END : Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet.
bits : 3 - 3 (1 bit)
access : read-write

SETUP_END : Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear.
bits : 4 - 4 (1 bit)
access : read-only

SEND_STALL : Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set.
bits : 5 - 5 (1 bit)
access : read-write

SERV_OUTPKTRDY : Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set.
bits : 6 - 6 (1 bit)
access : read-write

SERV_SETUP_END : Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set
bits : 7 - 7 (1 bit)
access : read-write


INCSRL

Control status lower register for INx endpoint (x == INDEX).
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
alternate_register : CSR0
reset_Mask : 0x0

INCSRL INCSRL read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INPKTRDY FIFONOTEMPTY UNDERRUN FLUSHFIFO SENDSTALL SENTSTALL CLRDATATOG INCOMPTX

INPKTRDY : IN Packet Ready. Write a 1 to clear
bits : 0 - 0 (1 bit)
access : read-only

FIFONOTEMPTY : Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear.
bits : 1 - 1 (1 bit)
access : read-write

UNDERRUN : Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear
bits : 2 - 2 (1 bit)
access : read-write

FLUSHFIFO : Flush Next Packet from IN FIFO. Write 1 to clear
bits : 3 - 3 (1 bit)
access : read-write

SENDSTALL : Send STALL Handshake.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : terminate

Terminate STALL handhsake

1 : respond

Respond to an IN token with a STALL handshake

End of enumeration elements list.

SENTSTALL : Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear.
bits : 5 - 5 (1 bit)
access : read-write

CLRDATATOG : Write 1 to clear IN endpoint data-toggle to 0.
bits : 6 - 6 (1 bit)
access : read-write

INCOMPTX : Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear.
bits : 7 - 7 (1 bit)
access : read-write


INCSRU

Control status upper register for INx endpoint (x == INDEX).
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INCSRU INCSRU read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 DPKTBUFDIS DMAREQMODE FRCDATATOG DMAREQEN MODE ISO AUTOSET

DPKTBUFDIS : Double Packet Buffering Disable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : en

Enable Double packet buffering.

1 : dis

Disable Double Packet Buffering.

End of enumeration elements list.

DMAREQMODE : DMA Request Mode Enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : 0

Enable DMA Request Mode 0.

1 : 1

Enable DMA Request Mode 1.

End of enumeration elements list.

FRCDATATOG : Force In Data - Toggle
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : received

Toggle data-toglge only when an ACK is received.

1 : dontcare

Toggle data-toggle regardless of ACK.

End of enumeration elements list.

DMAREQEN : DMA Request Enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : dis

Disable DMA for this IN endpoint.

1 : en

Enable DMA for this IN endpoint.

End of enumeration elements list.

MODE : Endpoint Direction Mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : out

Endpoint direction is OUT.

1 : in

Endpoint direction is IN.

End of enumeration elements list.

ISO : Isochronous Transfer Enable
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : interrupt

Enable IN Bulk and IN interrupt transfers.

1 : isochronous

Enable IN Isochronous transfers.

End of enumeration elements list.

AUTOSET : Auto Set inpktrdy.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : set

USBHS_INCSRL_inpktrdy must be set by firmware.

1 : auto

USBHS_INCSRL_inpktrdy is automatically set.

End of enumeration elements list.


OUTMAXP

Maximum packet size for OUTx endpoint (x == INDEX).
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OUTMAXP OUTMAXP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MAXPACKETSIZE NUMPACKMINUS1

MAXPACKETSIZE : Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9.
bits : 0 - 10 (11 bit)

NUMPACKMINUS1 : Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize.
bits : 11 - 15 (5 bit)


OUTCSRL

Control status lower register for OUTx endpoint (x == INDEX).
address_offset : 0x16 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OUTCSRL OUTCSRL read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 OUTPKTRDY FIFOFULL OVERRUN DATAERROR FLUSHFIFO SENDSTALL SENTSTALL CLRDATATOG

OUTPKTRDY :
bits : 0 - 0 (1 bit)
access : read-write

FIFOFULL :
bits : 1 - 1 (1 bit)
access : read-only

OVERRUN :
bits : 2 - 2 (1 bit)
access : read-write

DATAERROR :
bits : 3 - 3 (1 bit)
access : read-only

FLUSHFIFO :
bits : 4 - 4 (1 bit)
access : read-write

SENDSTALL :
bits : 5 - 5 (1 bit)
access : read-write

SENTSTALL :
bits : 6 - 6 (1 bit)
access : read-write

CLRDATATOG :
bits : 7 - 7 (1 bit)
access : read-write


OUTCSRU

Control status upper register for OUTx endpoint (x == INDEX).
address_offset : 0x17 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OUTCSRU OUTCSRU read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INCOMPRX DPKTBUFDIS DMAREQMODE DISNYET DMAREQEN ISO AUTOCLEAR

INCOMPRX :
bits : 0 - 0 (1 bit)
access : read-only

DPKTBUFDIS :
bits : 1 - 1 (1 bit)
access : read-write

DMAREQMODE :
bits : 3 - 3 (1 bit)
access : read-write

DISNYET :
bits : 4 - 4 (1 bit)
access : read-write

DMAREQEN :
bits : 5 - 5 (1 bit)
access : read-write

ISO :
bits : 6 - 6 (1 bit)
access : read-write

AUTOCLEAR :
bits : 7 - 7 (1 bit)
access : read-write


COUNT0

Number of received bytes in EP 0 FIFO (INDEX == 0).
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

COUNT0 COUNT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT0

COUNT0 : Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1
bits : 0 - 6 (7 bit)
access : read-only


OUTCOUNT

Number of received bytes in OUT EPx FIFO (x == INDEX).
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
alternate_register : COUNT0
reset_Mask : 0x0

OUTCOUNT OUTCOUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTCOUNT

OUTCOUNT : Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO.
bits : 0 - 12 (13 bit)
access : read-only


INTRIN

Interrupt register for EP0 and IN EP1-15.
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTRIN INTRIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_IN_INT EP1_IN_INT EP2_IN_INT EP3_IN_INT EP4_IN_INT EP5_IN_INT EP6_IN_INT EP7_IN_INT EP8_IN_INT EP9_IN_INT EP10_IN_INT EP11_IN_INT EP12_IN_INT EP13_IN_INT EP14_IN_INT EP15_IN_INT

EP0_IN_INT : Endpoint 0 interrupt.
bits : 0 - 0 (1 bit)
access : read-only

EP1_IN_INT : Endpoint 1 interrupt.
bits : 1 - 1 (1 bit)
access : read-only

EP2_IN_INT : Endpoint 2 interrupt.
bits : 2 - 2 (1 bit)
access : read-only

EP3_IN_INT : Endpoint 3 interrupt.
bits : 3 - 3 (1 bit)
access : read-only

EP4_IN_INT : Endpoint 4 interrupt.
bits : 4 - 4 (1 bit)
access : read-only

EP5_IN_INT : Endpoint 5 interrupt.
bits : 5 - 5 (1 bit)
access : read-only

EP6_IN_INT : Endpoint 6 interrupt.
bits : 6 - 6 (1 bit)
access : read-only

EP7_IN_INT : Endpoint 7 interrupt.
bits : 7 - 7 (1 bit)
access : read-only

EP8_IN_INT : Endpoint 8 interrupt.
bits : 8 - 8 (1 bit)
access : read-only

EP9_IN_INT : Endpoint 9 interrupt.
bits : 9 - 9 (1 bit)
access : read-only

EP10_IN_INT : Endpoint 10 interrupt.
bits : 10 - 10 (1 bit)
access : read-only

EP11_IN_INT : Endpoint 11 interrupt.
bits : 11 - 11 (1 bit)
access : read-only

EP12_IN_INT : Endpoint 12 interrupt.
bits : 12 - 12 (1 bit)
access : read-only

EP13_IN_INT : Endpoint 13 interrupt.
bits : 13 - 13 (1 bit)
access : read-only

EP14_IN_INT : Endpoint 14 interrupt.
bits : 14 - 14 (1 bit)
access : read-only

EP15_IN_INT : Endpoint 15 interrupt.
bits : 15 - 15 (1 bit)
access : read-only


FIFO0

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO0 FIFO0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO0

USBHS_FIFO0 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO1

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO1 FIFO1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO1

USBHS_FIFO1 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO2

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO2 FIFO2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO2

USBHS_FIFO2 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO3

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO3 FIFO3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO3

USBHS_FIFO3 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO4

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO4 FIFO4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO4

USBHS_FIFO4 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO5

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO5 FIFO5 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO5

USBHS_FIFO5 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO6

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO6 FIFO6 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO6

USBHS_FIFO6 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO7

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO7 FIFO7 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO7

USBHS_FIFO7 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


INTROUT

Interrupt register for OUT EP 1-15.
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTROUT INTROUT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP1_OUT_INT EP2_OUT_INT EP3_OUT_INT EP4_OUT_INT EP5_OUT_INT EP6_OUT_INT EP7_OUT_INT EP8_OUT_INT EP9_OUT_INT EP10_OUT_INT EP11_OUT_INT EP12_OUT_INT EP13_OUT_INT EP14_OUT_INT EP15_OUT_INT

EP1_OUT_INT : Endpoint 1 interrupt.
bits : 1 - 1 (1 bit)
access : read-only

EP2_OUT_INT : Endpoint 2 interrupt.
bits : 2 - 2 (1 bit)
access : read-only

EP3_OUT_INT : Endpoint 3 interrupt.
bits : 3 - 3 (1 bit)
access : read-only

EP4_OUT_INT : Endpoint 4 interrupt.
bits : 4 - 4 (1 bit)
access : read-only

EP5_OUT_INT : Endpoint 5 interrupt.
bits : 5 - 5 (1 bit)
access : read-only

EP6_OUT_INT : Endpoint 6 interrupt.
bits : 6 - 6 (1 bit)
access : read-only

EP7_OUT_INT : Endpoint 7 interrupt.
bits : 7 - 7 (1 bit)
access : read-only

EP8_OUT_INT : Endpoint 8 interrupt.
bits : 8 - 8 (1 bit)
access : read-only

EP9_OUT_INT : Endpoint 9 interrupt.
bits : 9 - 9 (1 bit)
access : read-only

EP10_OUT_INT : Endpoint 10 interrupt.
bits : 10 - 10 (1 bit)
access : read-only

EP11_OUT_INT : Endpoint 11 interrupt.
bits : 11 - 11 (1 bit)
access : read-only

EP12_OUT_INT : Endpoint 12 interrupt.
bits : 12 - 12 (1 bit)
access : read-only

EP13_OUT_INT : Endpoint 13 interrupt.
bits : 13 - 13 (1 bit)
access : read-only

EP14_OUT_INT : Endpoint 14 interrupt.
bits : 14 - 14 (1 bit)
access : read-only

EP15_OUT_INT : Endpoint 15 interrupt.
bits : 15 - 15 (1 bit)
access : read-only


FIFO8

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO8 FIFO8 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO8

USBHS_FIFO8 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


M31_PHY_PONRST

M31_PHY_PONRST
address_offset : 0x410 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M31_PHY_PONRST M31_PHY_PONRST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M31_PHY_NONCRY_RSTB

M31_PHY_NONCRY_RSTB
address_offset : 0x414 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M31_PHY_NONCRY_RSTB M31_PHY_NONCRY_RSTB read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M31_PHY_NONCRY_EN

M31_PHY_NONCRY_EN
address_offset : 0x418 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M31_PHY_NONCRY_EN M31_PHY_NONCRY_EN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M31_PHY_PLL_EN

M31_PHY_PLL_EN
address_offset : 0x430 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M31_PHY_PLL_EN M31_PHY_PLL_EN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M31_PHY_OSCOUTEN

M31_PHY_OSCOUTEN
address_offset : 0x43C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M31_PHY_OSCOUTEN M31_PHY_OSCOUTEN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FIFO9

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO9 FIFO9 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO9

USBHS_FIFO9 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


M31_PHY_CORECLKIN

M31_PHY_CORECLKIN
address_offset : 0x448 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M31_PHY_CORECLKIN M31_PHY_CORECLKIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M31_PHY_XTLSEL

M31_PHY_XTLSEL
address_offset : 0x44C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M31_PHY_XTLSEL M31_PHY_XTLSEL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

M31_PHY_OUTCLKSEL

M31_PHY_OUTCLKSEL
address_offset : 0x45C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

M31_PHY_OUTCLKSEL M31_PHY_OUTCLKSEL read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FIFO10

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO10 FIFO10 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO10

USBHS_FIFO10 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


MXM_INT

USB Added Maxim Interrupt Flag Register.
address_offset : 0x498 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MXM_INT MXM_INT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUS NOVBUS

VBUS : VBUS
bits : 0 - 0 (1 bit)

NOVBUS : NOVBUS
bits : 1 - 1 (1 bit)


MXM_INT_EN

USB Added Maxim Interrupt Enable Register.
address_offset : 0x49C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MXM_INT_EN MXM_INT_EN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUS NOVBUS

VBUS : VBUS
bits : 0 - 0 (1 bit)

NOVBUS : NOVBUS
bits : 1 - 1 (1 bit)


MXM_SUSPEND

USB Added Maxim Suspend Register.
address_offset : 0x4A0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MXM_SUSPEND MXM_SUSPEND read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEL

SEL : Suspend register
bits : 0 - 0 (1 bit)


MXM_REG_A4

USB Added Maxim Power Status Register
address_offset : 0x4A4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MXM_REG_A4 MXM_REG_A4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VRST_VDDB_N_A DMA_INT

VRST_VDDB_N_A : VRST_VDDB_N_A
bits : 0 - 0 (1 bit)

DMA_INT : DMA_INT
bits : 1 - 1 (1 bit)


FIFO11

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO11 FIFO11 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO11

USBHS_FIFO11 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO12

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO12 FIFO12 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO12

USBHS_FIFO12 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO13

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO13 FIFO13 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO13

USBHS_FIFO13 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO14

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO14 FIFO14 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO14

USBHS_FIFO14 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


FIFO15

Read for OUT data FIFO, write for IN data FIFO.
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FIFO15 FIFO15 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_FIFO15

USBHS_FIFO15 : USBHS Endpoint FIFO Read/Write Register.
bits : 0 - 31 (32 bit)


INTRINEN

Interrupt enable for EP 0 and IN EP 1-15.
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTRINEN INTRINEN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_INT_EN EP1_IN_INT_EN EP2_IN_INT_EN EP3_IN_INT_EN EP4_IN_INT_EN EP5_IN_INT_EN EP6_IN_INT_EN EP7_IN_INT_EN EP8_IN_INT_EN EP9_IN_INT_EN EP10_IN_INT_EN EP11_IN_INT_EN EP12_IN_INT_EN EP13_IN_INT_EN EP14_IN_INT_EN EP15_IN_INT_EN

EP0_INT_EN : Endpoint 0 interrupt enable.
bits : 0 - 0 (1 bit)
access : read-write

EP1_IN_INT_EN : Endpoint 1 interrupt enable.
bits : 1 - 1 (1 bit)
access : read-write

EP2_IN_INT_EN : Endpoint 2 interrupt enable.
bits : 2 - 2 (1 bit)
access : read-write

EP3_IN_INT_EN : Endpoint 3 interrupt enable.
bits : 3 - 3 (1 bit)
access : read-write

EP4_IN_INT_EN : Endpoint 4 interrupt enable.
bits : 4 - 4 (1 bit)
access : read-write

EP5_IN_INT_EN : Endpoint 5 interrupt enable.
bits : 5 - 5 (1 bit)
access : read-write

EP6_IN_INT_EN : Endpoint 6 interrupt enable.
bits : 6 - 6 (1 bit)
access : read-write

EP7_IN_INT_EN : Endpoint 7 interrupt enable.
bits : 7 - 7 (1 bit)
access : read-write

EP8_IN_INT_EN : Endpoint 8 interrupt enable.
bits : 8 - 8 (1 bit)
access : read-write

EP9_IN_INT_EN : Endpoint 9 interrupt enable.
bits : 9 - 9 (1 bit)
access : read-write

EP10_IN_INT_EN : Endpoint 10 interrupt enable.
bits : 10 - 10 (1 bit)
access : read-write

EP11_IN_INT_EN : Endpoint 11 interrupt enable.
bits : 11 - 11 (1 bit)
access : read-write

EP12_IN_INT_EN : Endpoint 12 interrupt enable.
bits : 12 - 12 (1 bit)
access : read-write

EP13_IN_INT_EN : Endpoint 13 interrupt enable.
bits : 13 - 13 (1 bit)
access : read-write

EP14_IN_INT_EN : Endpoint 14 interrupt enable.
bits : 14 - 14 (1 bit)
access : read-write

EP15_IN_INT_EN : Endpoint 15 interrupt enable.
bits : 15 - 15 (1 bit)
access : read-write


HWVERS

HWVERS
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWVERS HWVERS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHS_HWVERS

USBHS_HWVERS : USBHS Register.
bits : 0 - 15 (16 bit)


EPINFO

Endpoint hardware information.
address_offset : 0x78 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EPINFO EPINFO read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INTENDPOINTS OUTENDPOINTS

INTENDPOINTS :
bits : 0 - 3 (4 bit)
access : read-only

OUTENDPOINTS :
bits : 4 - 7 (4 bit)
access : read-only


RAMINFO

RAM width and DMA hardware information.
address_offset : 0x79 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RAMINFO RAMINFO read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RAMBITS DMACHANS

RAMBITS :
bits : 0 - 3 (4 bit)
access : read-only

DMACHANS :
bits : 4 - 7 (4 bit)
access : read-only


SOFTRESET

Software reset register.
address_offset : 0x7A Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SOFTRESET SOFTRESET read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RSTS RSTXS

RSTS :
bits : 0 - 0 (1 bit)
access : read-write

RSTXS :
bits : 1 - 1 (1 bit)
access : read-write


EARLYDMA

DMA timing control register.
address_offset : 0x7B Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EARLYDMA EARLYDMA read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 EDMAOUT EDMAIN

EDMAOUT :
bits : 0 - 0 (1 bit)
access : read-write

EDMAIN :
bits : 1 - 1 (1 bit)
access : read-write


INTROUTEN

Interrupt enable for OUT EP 1-15.
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTROUTEN INTROUTEN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP1_OUT_INT_EN EP2_OUT_INT_EN EP3_OUT_INT_EN EP4_OUT_INT_EN EP5_OUT_INT_EN EP6_OUT_INT_EN EP7_OUT_INT_EN EP8_OUT_INT_EN EP9_OUT_INT_EN EP10_OUT_INT_EN EP11_OUT_INT_EN EP12_OUT_INT_EN EP13_OUT_INT_EN EP14_OUT_INT_EN EP15_OUT_INT_EN

EP1_OUT_INT_EN : Endpoint 1 interrupt.
bits : 1 - 1 (1 bit)
access : read-write

EP2_OUT_INT_EN : Endpoint 2 interrupt.
bits : 2 - 2 (1 bit)
access : read-write

EP3_OUT_INT_EN : Endpoint 3 interrupt.
bits : 3 - 3 (1 bit)
access : read-write

EP4_OUT_INT_EN : Endpoint 4 interrupt.
bits : 4 - 4 (1 bit)
access : read-write

EP5_OUT_INT_EN : Endpoint 5 interrupt.
bits : 5 - 5 (1 bit)
access : read-write

EP6_OUT_INT_EN : Endpoint 6 interrupt.
bits : 6 - 6 (1 bit)
access : read-write

EP7_OUT_INT_EN : Endpoint 7 interrupt.
bits : 7 - 7 (1 bit)
access : read-write

EP8_OUT_INT_EN : Endpoint 8 interrupt.
bits : 8 - 8 (1 bit)
access : read-write

EP9_OUT_INT_EN : Endpoint 9 interrupt.
bits : 9 - 9 (1 bit)
access : read-write

EP10_OUT_INT_EN : Endpoint 10 interrupt.
bits : 10 - 10 (1 bit)
access : read-write

EP11_OUT_INT_EN : Endpoint 11 interrupt.
bits : 11 - 11 (1 bit)
access : read-write

EP12_OUT_INT_EN : Endpoint 12 interrupt.
bits : 12 - 12 (1 bit)
access : read-write

EP13_OUT_INT_EN : Endpoint 13 interrupt.
bits : 13 - 13 (1 bit)
access : read-write

EP14_OUT_INT_EN : Endpoint 14 interrupt.
bits : 14 - 14 (1 bit)
access : read-write

EP15_OUT_INT_EN : Endpoint 15 interrupt.
bits : 15 - 15 (1 bit)
access : read-write


CTUCH

Chirp timeout timer setting.
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTUCH CTUCH read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_T_UCH

C_T_UCH : HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host.
bits : 0 - 15 (16 bit)


CTHSRTN

Sets delay between HS resume to UTM normal operating mode.
address_offset : 0x82 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CTHSRTN CTHSRTN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C_T_HSTRN

C_T_HSTRN : High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation.
bits : 0 - 15 (16 bit)


INTRUSB

Interrupt register for common USB interrupts.
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTRUSB INTRUSB read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SUSPEND_INT RESUME_INT RESET_INT SOF_INT

SUSPEND_INT : Suspend detected.
bits : 0 - 0 (1 bit)
access : read-only

RESUME_INT : Resume detected.
bits : 1 - 1 (1 bit)
access : read-only

RESET_INT : Bus reset detected.
bits : 2 - 2 (1 bit)
access : read-only

SOF_INT : Start of Frame.
bits : 3 - 3 (1 bit)
access : read-only


INTRUSBEN

Interrupt enable for common USB interrupts.
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INTRUSBEN INTRUSBEN read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 SUSPEND_INT_EN RESUME_INT_EN RESET_INT_EN SOF_INT_EN

SUSPEND_INT_EN : Suspend detected.
bits : 0 - 0 (1 bit)
access : read-write

RESUME_INT_EN : Resume detected.
bits : 1 - 1 (1 bit)
access : read-write

RESET_INT_EN : Bus reset detected.
bits : 2 - 2 (1 bit)
access : read-write

SOF_INT_EN : Start of Frame.
bits : 3 - 3 (1 bit)
access : read-write


FRAME

Frame number.
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FRAME FRAME read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAMENUM

FRAMENUM : Read the last received frame number, that is the 11-bit frame number received in the SOF packet.
bits : 0 - 10 (11 bit)
access : read-only


INDEX

Index for banked registers.
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INDEX INDEX read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 INDEX

INDEX : Index Register Access Selector.
bits : 0 - 3 (4 bit)
access : read-write


TESTMODE

USB 2.0 test mode enable register.
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TESTMODE TESTMODE read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 TEST_SE0_NAK TEST_J TEST_K TEST_PKT FORCE_HS FORCE_FS

TEST_SE0_NAK : Respond to any valid IN token with NAK.
bits : 0 - 0 (1 bit)
access : read-write

TEST_J : Force USB to continuous J state.
bits : 1 - 1 (1 bit)
access : read-write

TEST_K : Force USB to continuous K state.
bits : 2 - 2 (1 bit)
access : read-write

TEST_PKT : Transmit fixed test packet.
bits : 3 - 3 (1 bit)
access : read-write

FORCE_HS : Force USB to High-speed after reset.
bits : 4 - 4 (1 bit)
access : read-write

FORCE_FS : Force USB to Full-speed after reset.
bits : 5 - 5 (1 bit)
access : read-write



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