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MCR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ECCEN

CTRL

HIRC96M

OUTEN

AINCOMP


ECCEN

ECC Enable Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECCEN ECCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSRAM0ECCEN SYSRAM1ECCEN SYSRAM2ECCEN SYSRAM3ECCEN SYSRAM4ECCEN SYSRAM5ECCEN IC0ECCEN IC1ECCEN ICXIPECCEN FL0ECCEN FL1ECCEN

SYSRAM0ECCEN : ECC System RAM Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

SYSRAM1ECCEN : ECC System RAM Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

SYSRAM2ECCEN : ECC System RAM Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

SYSRAM3ECCEN : ECC System RAM Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

SYSRAM4ECCEN : ECC System RAM Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

SYSRAM5ECCEN : ECC System RAM Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

IC0ECCEN : Icache0 ECC Enable.
bits : 8 - 8 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

IC1ECCEN : Icache1 ECC Enable.
bits : 9 - 9 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

ICXIPECCEN : IcacheXIP ECC Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

FL0ECCEN : Flash0 ECC Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

FL1ECCEN : Flash1 ECC Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.


CTRL

Misc Power State Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDDCSWEN VDDCSW USBSWEN_N BUCKCLKSCALEN P1M VDDIOH_SEL

VDDCSWEN : Allows switching VDDC from VCOREA to VCOREB
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

VDDCSW : Controls switching of VCORE
bits : 1 - 2 (2 bit)

USBSWEN_N : USB Switch Control
bits : 3 - 3 (1 bit)

Enumeration:

1 : off

USB SW off in LP modes

0 : on

USB SW On

End of enumeration elements list.

BUCKCLKSCALEN : Allows Dynamic scaling of SIMO clock, reduces power in LP Modes
bits : 8 - 8 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

P1M : Enable the Reset Pad Pull Up Resistors
bits : 9 - 9 (1 bit)

Enumeration:

0 : 1m

1MOhm Pullup

1 : 25k

25kOhm Pullup.

End of enumeration elements list.

VDDIOH_SEL : Error! Description not Found!
bits : 10 - 10 (1 bit)


HIRC96M

96MHz Oscillator Trim Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIRC96M HIRC96M read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIRC96MTR

HIRC96MTR : Allows User to Trim 96MHz Oscillator
bits : 0 - 7 (8 bit)


OUTEN

GPIOOUT_EN Function Enable Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTEN OUTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQWOUT0EN SQWOUT1EN PDOWNOUT0EN PDOWNOUT1EN

SQWOUT0EN : Allows SQWOUT on GPIO0_19
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

SQWOUT1EN : Allows SQWOUT on GPIO0_27
bits : 1 - 1 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

PDOWNOUT0EN : Allows PDOWN on GPIO0_18
bits : 2 - 2 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.

PDOWNOUT1EN : Allows PDOWN on GPIO0_26
bits : 3 - 3 (1 bit)

Enumeration:

0 : dis

disabled.

1 : en

enabled.

End of enumeration elements list.


AINCOMP

Comparator Power Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AINCOMP AINCOMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AINCOMP0PD AINCOMP1PD AINCOMP2PD AINCOMP3PD AINCOMPHYST

AINCOMP0PD : Power Down AIN Comp0
bits : 0 - 0 (1 bit)

Enumeration:

0 : on

power on

1 : off

power off

End of enumeration elements list.

AINCOMP1PD : Power Down AIN Comp1
bits : 1 - 1 (1 bit)

Enumeration:

0 : on

power on

1 : off

power off

End of enumeration elements list.

AINCOMP2PD : Power Down AIN Comp2
bits : 2 - 2 (1 bit)

Enumeration:

0 : on

power on

1 : off

power off

End of enumeration elements list.

AINCOMP3PD : Power Down AIN Comp3
bits : 3 - 3 (1 bit)

Enumeration:

0 : on

power on

1 : off

power off

End of enumeration elements list.

AINCOMPHYST : Set Hysteresis on Analog Comparators
bits : 4 - 5 (2 bit)



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