Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Cache ID Register.
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RELNUM : Release Number. Identifies the RTL release version.
bits : 0 - 5 (6 bit)
PARTNUM : Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.
bits : 6 - 9 (4 bit)
CCHID : Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.
bits : 10 - 15 (6 bit)
Cache Control and Status Register.
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHE_EN : Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.
1 : en
Cache Enabled.
End of enumeration elements list.
WRITE_ALLOC_EN : Write Allocate Enable. This bit only writable while the cache is disabled.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Write-no-allocate.
1 : en
Write-allocate enabled.
End of enumeration elements list.
CWFST_DIS : Critical word first and streaming disable. This bit only writeable while the cache is disabled.
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Critical word first and streaming disabled.
0 : en
Critical word first and streaming enabled.
End of enumeration elements list.
CACHE_RDY : Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.
bits : 16 - 16 (1 bit)
Enumeration:
0 : notReady
Not Ready.
1 : ready
Ready.
End of enumeration elements list.
Memory Configuration Register.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CCHSZ : Cache Size. Indicates total size in Kbytes of cache.
bits : 0 - 15 (16 bit)
MEMSZ : Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.
bits : 16 - 31 (16 bit)
Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0.
address_offset : 0x700 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IA : Invalidate all cache contents.
bits : 0 - 31 (32 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.