CTL

ADJ_UP

ADJ_DWN

THRES_CMP

TAP_SEL

TAP_SEL0

STAT

TAP_SEL1

TAP_SEL2

DIRECT

TAP_SEL3

MON

TAP_SEL4

MON_ENA : Enable the DVS monitoring circuit
bits : 0 - 0 (1 bit)

ADJ_ENA : Enable the power supply adjustment based on measurements
bits : 1 - 1 (1 bit)

PS_FB_DIS : Power Supply Feedback Disable
bits : 2 - 2 (1 bit)

CTRL_TAP_ENA : Use the TAP Select for automatic adjustment or monitoring
bits : 3 - 3 (1 bit)

PROP_DLY : Additional delay to monitor lines
bits : 4 - 5 (2 bit)

MON_ONESHOT : Measure delay once
bits : 6 - 6 (1 bit)

GO_DIRECT : Operate in automatic mode or move directly
bits : 7 - 7 (1 bit)

DIRECT_REG : Step incrementally to target voltage
bits : 8 - 8 (1 bit)

PRIME_ENA : Include a delay line priming signal before monitoring
bits : 9 - 9 (1 bit)

LIMIT_IE : Enable Limit Error Interrupt
bits : 10 - 10 (1 bit)

RANGE_IE : Enable Range Error Interrupt
bits : 11 - 11 (1 bit)

ADJ_IE : Enable Adjustment Error Interrupt
bits : 12 - 12 (1 bit)

REF_SEL : Select TAP used for voltage adjustment
bits : 13 - 16 (4 bit)

INC_VAL : Step size to increment voltage when in automatic mode
bits : 17 - 19 (3 bit)

DVS_PS_APB_DIS : Prevent the application code from adjusting Vcore
bits : 20 - 20 (1 bit)

DVS_HI_RANGE_ANY : Any high range signal from a delay line will cause a voltage adjustment
bits : 21 - 21 (1 bit)

FB_TO_IE : Enable Voltage Adjustment Timeout Interrupt
bits : 22 - 22 (1 bit)

FC_LV_IE : Enable Low Voltage Interrupt
bits : 23 - 23 (1 bit)

PD_ACK_ENA : Prevent DVS from ack'ing a request to enter a low power mode until in the idle state
bits : 24 - 24 (1 bit)

ADJ_ABORT : Causes the DVS to enter the idle state immediately on a request to enter a low power mode
bits : 25 - 25 (1 bit)

DLY : Number of prescaled clocks between updates of the adjustment delay counter
bits : 0 - 15 (16 bit)

PRE : Number of clocks before DVS_ADJ_UP_DLY is decremented
bits : 16 - 23 (8 bit)

DLY : Number of prescaled clocks between updates of the adjustment delay counter
bits : 0 - 15 (16 bit)

PRE : Number of clocks before DVS_ADJ_DWN_DLY is decremented
bits : 16 - 23 (8 bit)

VCNTR_THRES_CNT : Value used to determine 'low voltage' range
bits : 0 - 6 (7 bit)

VCNTR_THRES_MASK : Mask applied to threshold and vcount to determine if the device is in a low voltage range
bits : 8 - 14 (7 bit)

LO : Select delay line tap for lower bound of auto adjustment
bits : 0 - 4 (5 bit)

LO_TAP_STAT : Returns last delay line tap value
bits : 5 - 5 (1 bit)

CTR_TAP_STAT : Returns last delay line tap value
bits : 6 - 6 (1 bit)

HI_TAP_STAT : Returns last delay line tap value
bits : 7 - 7 (1 bit)

HI : Selects delay line tap for high point of auto adjustment
bits : 8 - 12 (5 bit)

CTR : Selects delay line tap for center point of auto adjustment
bits : 16 - 20 (5 bit)

COARSE : Selects delay line tap for coarse or fixed delay portion of the line
bits : 24 - 26 (3 bit)

DET_DLY : Number of HCLK between delay line launch and sampling
bits : 29 - 30 (2 bit)

DELAY_ACT : Set if the delay is active
bits : 31 - 31 (1 bit)

LO : Select delay line tap for lower bound of auto adjustment
bits : 0 - 4 (5 bit)

LO_TAP_STAT : Returns last delay line tap value
bits : 5 - 5 (1 bit)

CTR_TAP_STAT : Returns last delay line tap value
bits : 6 - 6 (1 bit)

HI_TAP_STAT : Returns last delay line tap value
bits : 7 - 7 (1 bit)

HI : Selects delay line tap for high point of auto adjustment
bits : 8 - 12 (5 bit)

CTR : Selects delay line tap for center point of auto adjustment
bits : 16 - 20 (5 bit)

COARSE : Selects delay line tap for coarse or fixed delay portion of the line
bits : 24 - 26 (3 bit)

DET_DLY : Number of HCLK between delay line launch and sampling
bits : 29 - 30 (2 bit)

DELAY_ACT : Set if the delay is active
bits : 31 - 31 (1 bit)

DVS_STATE : State machine state
bits : 0 - 3 (4 bit)

ADJ_UP_ENA : DVS Raising voltage
bits : 4 - 4 (1 bit)

ADJ_DWN_ENA : DVS Lowering voltage
bits : 5 - 5 (1 bit)

ADJ_ACTIVE : Adjustment to a Direct Voltage
bits : 6 - 6 (1 bit)

CTR_TAP_OK : Tap Enabled and the Tap is withing Hi/Low limits
bits : 7 - 7 (1 bit)

CTR_TAP_SEL : Status of selected center tap delay line detect output
bits : 8 - 8 (1 bit)

SLOW_TRIP_DET : Provides the current combined status of all selected Low Range delay lines
bits : 9 - 9 (1 bit)

FAST_TRIP_DET : Provides the current combined status of all selected High Range delay lines
bits : 10 - 10 (1 bit)

PS_IN_RANGE : Indicates if the power supply is in range
bits : 11 - 11 (1 bit)

PS_VCNTR : Voltage Count value sent to the power supply
bits : 12 - 18 (7 bit)

MON_DLY_OK : Indicates the monitor delay count is at 0
bits : 19 - 19 (1 bit)

ADJ_DLY_OK : Indicates the adjustment delay count is at 0
bits : 20 - 20 (1 bit)

LO_LIMIT_DET : Power supply voltage counter is at low limit
bits : 21 - 21 (1 bit)

HI_LIMIT_DET : Power supply voltage counter is at high limit
bits : 22 - 22 (1 bit)

VALID_TAP : At least one delay line has been enabled
bits : 23 - 23 (1 bit)

LIMIT_ERR : Interrupt flag that indicates a voltage count is at/beyond manufacturer limits
bits : 24 - 24 (1 bit)

RANGE_ERR : Interrupt flag that indicates a tap has an invalid value
bits : 25 - 25 (1 bit)

ADJ_ERR : Interrupt flag that indicates up and down adjustment requested simultaneously
bits : 26 - 26 (1 bit)

REF_SEL_ERR : Indicates the ref select register bit is out of range
bits : 27 - 27 (1 bit)

REF_SEL_ERR : Indicates the ref select register bit is out of range
bits : 27 - 27 (1 bit)

FB_TO_ERR : Interrupt flag that indicates a timeout while adjusting the voltage
bits : 28 - 28 (1 bit)

FB_TO_ERR_S : Interrupt flag that mirror FB_TO_ERR and is write one clear
bits : 29 - 29 (1 bit)

FC_LV_DET_INT : Interrupt flag that indicates the power supply voltage requested is below the low threshold
bits : 30 - 30 (1 bit)

FC_LV_DET_S : Interrupt flag that mirrors FC_LV_DET_INT
bits : 31 - 31 (1 bit)

LO : Select delay line tap for lower bound of auto adjustment
bits : 0 - 4 (5 bit)

LO_TAP_STAT : Returns last delay line tap value
bits : 5 - 5 (1 bit)

CTR_TAP_STAT : Returns last delay line tap value
bits : 6 - 6 (1 bit)

HI_TAP_STAT : Returns last delay line tap value
bits : 7 - 7 (1 bit)

HI : Selects delay line tap for high point of auto adjustment
bits : 8 - 12 (5 bit)

CTR : Selects delay line tap for center point of auto adjustment
bits : 16 - 20 (5 bit)

COARSE : Selects delay line tap for coarse or fixed delay portion of the line
bits : 24 - 26 (3 bit)

DET_DLY : Number of HCLK between delay line launch and sampling
bits : 29 - 30 (2 bit)

DELAY_ACT : Set if the delay is active
bits : 31 - 31 (1 bit)

LO : Select delay line tap for lower bound of auto adjustment
bits : 0 - 4 (5 bit)

LO_TAP_STAT : Returns last delay line tap value
bits : 5 - 5 (1 bit)

CTR_TAP_STAT : Returns last delay line tap value
bits : 6 - 6 (1 bit)

HI_TAP_STAT : Returns last delay line tap value
bits : 7 - 7 (1 bit)

HI : Selects delay line tap for high point of auto adjustment
bits : 8 - 12 (5 bit)

CTR : Selects delay line tap for center point of auto adjustment
bits : 16 - 20 (5 bit)

COARSE : Selects delay line tap for coarse or fixed delay portion of the line
bits : 24 - 26 (3 bit)

DET_DLY : Number of HCLK between delay line launch and sampling
bits : 29 - 30 (2 bit)

DELAY_ACT : Set if the delay is active
bits : 31 - 31 (1 bit)

VOLTAGE : Sets the target power supply value
bits : 0 - 6 (7 bit)

LO : Select delay line tap for lower bound of auto adjustment
bits : 0 - 4 (5 bit)

LO_TAP_STAT : Returns last delay line tap value
bits : 5 - 5 (1 bit)

CTR_TAP_STAT : Returns last delay line tap value
bits : 6 - 6 (1 bit)

HI_TAP_STAT : Returns last delay line tap value
bits : 7 - 7 (1 bit)

HI : Selects delay line tap for high point of auto adjustment
bits : 8 - 12 (5 bit)

CTR : Selects delay line tap for center point of auto adjustment
bits : 16 - 20 (5 bit)

COARSE : Selects delay line tap for coarse or fixed delay portion of the line
bits : 24 - 26 (3 bit)

DET_DLY : Number of HCLK between delay line launch and sampling
bits : 29 - 30 (2 bit)

DELAY_ACT : Set if the delay is active
bits : 31 - 31 (1 bit)

DLY : Number of prescaled clocks between delay line samples
bits : 0 - 23 (24 bit)

PRE : Number of clocks before DVS_MON_DLY is decremented
bits : 24 - 31 (8 bit)

LO : Select delay line tap for lower bound of auto adjustment
bits : 0 - 4 (5 bit)

LO_TAP_STAT : Returns last delay line tap value
bits : 5 - 5 (1 bit)

CTR_TAP_STAT : Returns last delay line tap value
bits : 6 - 6 (1 bit)

HI_TAP_STAT : Returns last delay line tap value
bits : 7 - 7 (1 bit)

HI : Selects delay line tap for high point of auto adjustment
bits : 8 - 12 (5 bit)

CTR : Selects delay line tap for center point of auto adjustment
bits : 16 - 20 (5 bit)

COARSE : Selects delay line tap for coarse or fixed delay portion of the line
bits : 24 - 26 (3 bit)

DET_DLY : Number of HCLK between delay line launch and sampling
bits : 29 - 30 (2 bit)

DELAY_ACT : Set if the delay is active
bits : 31 - 31 (1 bit)