SCON

PCKDIV

PERCKCN0

MEMCKCN

MEMZCN

SCCK

MPRI0

MPRI1

RSTR0

SYSST

RSTR1

PERCKCN1

EVTEN

REVISION

SYSSIE

ECCERR

ECCNDED

ECCIRQEN

ECCERRAD

BTLELDOCN

BTLELDODLY

CLKCN

GP0

APBASYNC

PM

BSTAPEN : Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

SBUSARB : System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.
bits : 1 - 2 (2 bit)

Enumeration:

End of enumeration elements list.

FLASH_PAGE_FLIP : Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

CCACHE_FLUSH : Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4.
bits : 6 - 6 (1 bit)

Enumeration:

End of enumeration elements list.

DCACHE_FLUSH : Data Cache Flush. The system cache(s) will be flushed when this bit is set.
bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

DCACHE_DIS : Data Cache Disable. The system cache(s) will be completely disabled when this bit is set.
bits : 9 - 9 (1 bit)

Enumeration:

End of enumeration elements list.

CCHK : Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.
bits : 13 - 13 (1 bit)

Enumeration:

End of enumeration elements list.

CHKRES : ROM Checksum Result. This bit is only valid when CHKRD=1.
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

OVR : Operating Voltage Range. Setting these bits according to the VCore voltage allows the on-chip Random-Access memories to operate in their optimal timing range.
bits : 16 - 17 (2 bit)

Enumeration:

End of enumeration elements list.

PCF : These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware. These bits determine the clock frequency for the UART, I2C and Key Pad peripherals. These peripherals have an adaptive clock generator that dynamically adjusts the peripheral frequency based on the main system bus frequency. These bits are dynamically updated when the PLL0 is selected as the system clock source and are set by hardware.
bits : 0 - 2 (3 bit)

Enumeration:

End of enumeration elements list.

SDHCFRQ : SDHC Clock Frequency. This bits defines the clock frequency of SDHC.
bits : 7 - 7 (1 bit)

Enumeration:

End of enumeration elements list.

ADCFRQ : ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK/(ADCFRQ).
bits : 10 - 13 (4 bit)

AONCD : Always-ON(AON) domain CLock Divider. These bits define the AON domain clock divider.
bits : 14 - 15 (2 bit)

Enumeration:

End of enumeration elements list.

GPIO0D : GPIO0 Disable.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

GPIO1D : GPIO1 Disable.
bits : 1 - 1 (1 bit)

USBD : USB Disable.
bits : 3 - 3 (1 bit)

DMAD : DMA Disable.
bits : 5 - 5 (1 bit)

SPI0D : SPI 0 Disable.
bits : 6 - 6 (1 bit)

SPI1D : SPI 1 Disable.
bits : 7 - 7 (1 bit)

UART0D : UART 0 Disable.
bits : 9 - 9 (1 bit)

UART1D : UART 1 Disable.
bits : 10 - 10 (1 bit)

I2C0D : I2C 0 Disable.
bits : 13 - 13 (1 bit)

CRYPTOD : Crypto Disable.
bits : 14 - 14 (1 bit)

T0D : Timer 0 Disable.
bits : 15 - 15 (1 bit)

T1D : Timer 1 Disable.
bits : 16 - 16 (1 bit)

T2D : Timer 2 Disable.
bits : 17 - 17 (1 bit)

T3D : Timer 3 Disable.
bits : 18 - 18 (1 bit)

T4D : Timer 4 Disable.
bits : 19 - 19 (1 bit)

T5D : Timer 5 Disable.
bits : 20 - 20 (1 bit)

ADCD : ADC Disable.
bits : 23 - 23 (1 bit)

I2C1D : I2C 1 Disable.
bits : 28 - 28 (1 bit)

PTD : PT Clock Disable.
bits : 29 - 29 (1 bit)

SPIXIPD : SPI XiP Disable.
bits : 30 - 30 (1 bit)

SPIMD : SPI XiP Master Controller Disable.
bits : 31 - 31 (1 bit)

FWS : Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.
bits : 0 - 2 (3 bit)

SYSRAM0LS : System RAM 0 Light Sleep Mode.
bits : 16 - 16 (1 bit)

Enumeration:

End of enumeration elements list.

SYSRAM1LS : System RAM 1 Light Sleep Mode.
bits : 17 - 17 (1 bit)

SYSRAM2LS : System RAM 2 Light Sleep Mode.
bits : 18 - 18 (1 bit)

SYSRAM3LS : System RAM 3 Light Sleep Mode.
bits : 19 - 19 (1 bit)

SYSRAM4LS : System RAM 4 Light Sleep Mode.
bits : 20 - 20 (1 bit)

SYSRAM5LS : System RAM 5 Light Sleep Mode.
bits : 21 - 21 (1 bit)

SYSRAM6LS : System RAM 6 Light Sleep Mode.
bits : 22 - 22 (1 bit)

ICACHELS : ICache RAM Light Sleep Mode.
bits : 24 - 24 (1 bit)

ICACHEXIPLS : ICACHE-XIP RAM Light Sleep Mode.
bits : 25 - 25 (1 bit)

SCACHELS : SysCache RAM Light Sleep Mode.
bits : 26 - 26 (1 bit)

CRYPTOLS : CRYPTO RAM Light Sleep Mode.
bits : 27 - 27 (1 bit)

USBLS : USB FIFO Light Sleep Mode.
bits : 28 - 28 (1 bit)

ROMLS : ROM Light Sleep Mode.
bits : 29 - 29 (1 bit)

ROM1LS : ROM1 Light Sleep Mode.
bits : 30 - 30 (1 bit)

ICACHE1LS : ICache RAM Light Sleep Mode.
bits : 31 - 31 (1 bit)

SRAM0Z : System RAM Block 0.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

SRAM1Z : System RAM Block 1.
bits : 1 - 1 (1 bit)

SRAM2Z : System RAM Block 2.
bits : 2 - 2 (1 bit)

SRAM3Z : System RAM Block 3.
bits : 3 - 3 (1 bit)

SRAM4Z : System RAM Block 4.
bits : 4 - 4 (1 bit)

SRAM5Z : System RAM Block 5.
bits : 5 - 5 (1 bit)

SRAM6Z : System RAM Block 6.
bits : 6 - 6 (1 bit)

ICACHEZ : Instruction Cache.
bits : 8 - 8 (1 bit)

ICACHEXIPZ : Instruction Cache XIP Data and Tag Ram zeroizatoin.
bits : 9 - 9 (1 bit)

SCACHEDATAZ : System Cache Data Ram Zeroization.
bits : 10 - 10 (1 bit)

SCACHETAGZ : System Cache Tag Zeroization.
bits : 11 - 11 (1 bit)

CRYPTOZ : Crypto (MAA) Memory.
bits : 12 - 12 (1 bit)

USBFIFOZ : USB FIFO Zeroizatoin.
bits : 13 - 13 (1 bit)

ICACHE1Z : Instruction Cache.
bits : 14 - 14 (1 bit)

DMA : DMA Reset.
bits : 0 - 0 (1 bit)

Enumeration: reset ( read-write )

End of enumeration elements list.

WDT : Watchdog Timer Reset.
bits : 1 - 1 (1 bit)

GPIO0 : GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.
bits : 2 - 2 (1 bit)

GPIO1 : GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.
bits : 3 - 3 (1 bit)

TIMER0 : Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.
bits : 5 - 5 (1 bit)

TIMER1 : Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.
bits : 6 - 6 (1 bit)

TIMER2 : Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.
bits : 7 - 7 (1 bit)

TIMER3 : Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.
bits : 8 - 8 (1 bit)

TIMER4 : Timer3 Reset. Setting this bit to 1 resets Timer 4 blocks.
bits : 9 - 9 (1 bit)

TIMER5 : Timer3 Reset. Setting this bit to 1 resets Timer 5 blocks.
bits : 10 - 10 (1 bit)

UART0 : UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.
bits : 11 - 11 (1 bit)

UART1 : UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.
bits : 12 - 12 (1 bit)

SPI0 : SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.
bits : 13 - 13 (1 bit)

SPI1 : SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.
bits : 14 - 14 (1 bit)

I2C0 : I2C0 Reset.
bits : 16 - 16 (1 bit)

RTC : Real Time Clock Reset.
bits : 17 - 17 (1 bit)

CRYPTO : Cryptographic Reset. Setting this bit to 1 resets the AES block, the SHA block and the DES block.
bits : 18 - 18 (1 bit)

SMPHR : SMPHR Reset. Setting this bit to 1 resets the SMPHR block.
bits : 22 - 22 (1 bit)

USB : USB Reset. Setting this bit resets both USB blocks.
bits : 23 - 23 (1 bit)

TRNG : TRNG Reset.
bits : 24 - 24 (1 bit)

ADC : Analog to Digital Reset.
bits : 26 - 26 (1 bit)

DMA1 : DMA 1 Reset.
bits : 27 - 27 (1 bit)

UART2 : UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.
bits : 28 - 28 (1 bit)

SRST : Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.
bits : 29 - 29 (1 bit)

PRST : Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.
bits : 30 - 30 (1 bit)

SYSTEM : System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.
bits : 31 - 31 (1 bit)

ICECLOCK : ARM ICE Lock Status.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

CODEINTERR : Code Integrity Error Flag. This bit indicates a code integrity error has occured in XiP interface.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

SCMEMF : System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface.
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

I2C1 : I2C1 Reset.
bits : 0 - 0 (1 bit)

Enumeration: reset_read ( read )

End of enumeration elements list.

PT : PT Reset.
bits : 1 - 1 (1 bit)

PBM : PBM Reset.
bits : 2 - 2 (1 bit)

SPIXIP : SPI XiP Master Reset.
bits : 3 - 3 (1 bit)

XSPIM : GSPI XiP Master Controller Reset.
bits : 4 - 4 (1 bit)

GPIO3 : GPIO3 Reset.
bits : 5 - 5 (1 bit)

SDHC : SDHC/SDIO Reset.
bits : 6 - 6 (1 bit)

OWIRE : OWIRE Reset.
bits : 7 - 7 (1 bit)

WDT1 : WDT1 Reset.
bits : 8 - 8 (1 bit)

QSPI0_AHB : QSPI0_AHB Reset.
bits : 9 - 9 (1 bit)

SPIXMEM : SPIXMEM Reset.
bits : 15 - 15 (1 bit)

SMPHR : SMPHR Reset.
bits : 16 - 16 (1 bit)

WDT2 : WDT2 Reset.
bits : 17 - 17 (1 bit)

BTLE : BTLE Reset.
bits : 18 - 18 (1 bit)

AUDIO : AUDIO Reset.
bits : 19 - 19 (1 bit)

I2C2 : I2C2 Reset.
bits : 20 - 20 (1 bit)

HTMR0 : HTMR0 Reset.
bits : 22 - 22 (1 bit)

HTMR1 : HTMR1 Reset.
bits : 23 - 23 (1 bit)

DVS : DVS Reset.
bits : 24 - 24 (1 bit)

SIMO : SIMO Reset.
bits : 25 - 25 (1 bit)

BTLED : BTLE Disable.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

UART2D : UART2 Disable.
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

TRNGD : TRNG Disable.
bits : 2 - 2 (1 bit)

SCACHED : System Cache Clock Disable.
bits : 7 - 7 (1 bit)

SDMAD : SDMA Clock Disable.
bits : 8 - 8 (1 bit)

SMPHRD : Semaphore Clock Disable.
bits : 9 - 9 (1 bit)

SDHCD : SDHC/SDIO Clock Disable.
bits : 10 - 10 (1 bit)

ICACHEXIPD : ICache XIP Clock Disable.
bits : 12 - 12 (1 bit)

OWIRED : One-Wire Clock Disable.
bits : 13 - 13 (1 bit)

SPI3D : SPI3 Clock Disable.
bits : 14 - 14 (1 bit)

SPIXIPDD : SPI-XIP Data Clock Disable
bits : 20 - 20 (1 bit)

DMA1 : DMA1 Clock Disable
bits : 21 - 21 (1 bit)

AUDIO : AUDIO Clock Disable
bits : 23 - 23 (1 bit)

I2C2 : I2C 2 Clock Disable
bits : 24 - 24 (1 bit)

HTMR0 : HTMR 0 Clock Disable
bits : 25 - 25 (1 bit)

HTMR1 : HTMR 1 Clock Disable
bits : 26 - 26 (1 bit)

WDT0 : WDT0 Clock Disable
bits : 27 - 27 (1 bit)

WDT1 : WDT1 Clock Disable
bits : 28 - 28 (1 bit)

WDT2 : WDT2 Clock Disable
bits : 29 - 29 (1 bit)

CPU1 : CPU1 Clock Disable
bits : 31 - 31 (1 bit)

CPU0DMAEVENT : Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.
bits : 0 - 0 (1 bit)

CPU0RXEVENT : Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode.
bits : 1 - 1 (1 bit)

CPU0TXEVENT : Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].
bits : 2 - 2 (1 bit)

CPU1DMAEVENT : Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.
bits : 3 - 3 (1 bit)

CPU1RXEVENT : Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode.
bits : 4 - 4 (1 bit)

CPU1TXEVENT : Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25].
bits : 5 - 5 (1 bit)

REVISION : Manufacturer Chip Revision.
bits : 0 - 15 (16 bit)

ICEULIE : ARM ICE Unlock Interrupt Enable.
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

CIEIE : Code Integrity Error Interrupt Enable.
bits : 1 - 1 (1 bit)

SCMFIE : System Cache Memory Fault Interrupt Enable.
bits : 5 - 5 (1 bit)

SYSRAM0ECCERR : ECC System RAM0 Error Flag. Write 1 to clear.
bits : 0 - 0 (1 bit)

SYSRAM1ECCERR : ECC System RAM1 Error Flag. Write 1 to clear.
bits : 1 - 1 (1 bit)

SYSRAM2ECCERR : ECC System RAM2 Error Flag. Write 1 to clear.
bits : 2 - 2 (1 bit)

SYSRAM3ECCERR : ECC System RAM3 Error Flag. Write 1 to clear.
bits : 3 - 3 (1 bit)

SYSRAM4ECCERR : ECC System RAM4 Error Flag. Write 1 to clear.
bits : 4 - 4 (1 bit)

SYSRAM5ECCERR : ECC System RAM5 Error Flag. Write 1 to clear.
bits : 5 - 5 (1 bit)

SYSRAM6ECCERR : ECC System RAM6 Error Flag. Write 1 to clear.
bits : 6 - 6 (1 bit)

IC0ECCERR : ECC Icache0 Error Flag. Write 1 to clear.
bits : 8 - 8 (1 bit)

IC1ECCERR : ECC Icache1 Error Flag. Write 1 to clear.
bits : 9 - 9 (1 bit)

ICXIPECCERR : ECC IcacheXIP Error Flag. Write 1 to clear.
bits : 10 - 10 (1 bit)

FL0ECCERR : ECC Flash0 Error Flag. Write 1 to clear.
bits : 11 - 11 (1 bit)

FL1ECCERR : ECC Flash1 Error Flag. Write 1 to clear.
bits : 12 - 12 (1 bit)

SYSRAM0ECCNDED : ECC System RAM0 Error Flag. Write 1 to clear.
bits : 0 - 0 (1 bit)

SYSRAM1ECCNDED : ECC System RAM1 Not Double Error Detect. Write 1 to clear.
bits : 1 - 1 (1 bit)

SYSRAM2ECCNDED : ECC System RAM2 Not Double Error Detect. Write 1 to clear.
bits : 2 - 2 (1 bit)

SYSRAM3ECCNDED : ECC System RAM3 Not Double Error Detect. Write 1 to clear.
bits : 3 - 3 (1 bit)

SYSRAM4ECCNDED : ECC System RAM4 Not Double Error Detect. Write 1 to clear.
bits : 4 - 4 (1 bit)

SYSRAM5ECCNDED : ECC System RAM5 Not Double Error Detect. Write 1 to clear.
bits : 5 - 5 (1 bit)

SYSRAM6ECCNDED : ECC System RAM6 Not Double Error Detect. Write 1 to clear.
bits : 6 - 6 (1 bit)

IC0ECCNDED : ECC Icache0 Not Double Error Detect. Write 1 to clear.
bits : 8 - 8 (1 bit)

IC1ECCNDED : ECC Icache1 Not Double Error Detect. Write 1 to clear.
bits : 9 - 9 (1 bit)

ICXIPECCNDED : ECC IcacheXIP Not Double Error Detect. Write 1 to clear.
bits : 10 - 10 (1 bit)

FL0ECCNDED : ECC Flash0 Not Double Error Detect. Write 1 to clear.
bits : 11 - 11 (1 bit)

FL1ECCNDED : ECC Flash1 Not Double Error Detect. Write 1 to clear.
bits : 12 - 12 (1 bit)

SYSRAM0ECCEN : ECC System RAM0 Error Interrup Enable
bits : 0 - 0 (1 bit)

SYSRAM1ECCEN : ECC System RAM1 Error Interrup Enable
bits : 1 - 1 (1 bit)

SYSRAM2ECCEN : ECC System RAM2 Error Interrup Enable
bits : 2 - 2 (1 bit)

SYSRAM3ECCEN : ECC System RAM3 Error Interrup Enable
bits : 3 - 3 (1 bit)

SYSRAM4ECCEN : ECC System RAM4 Error Interrup Enable
bits : 4 - 4 (1 bit)

SYSRAM5ECCEN : ECC System RAM5 Error Interrup Enable
bits : 5 - 5 (1 bit)

SYSRAM6ECCEN : ECC System RAM6 Error Interrup Enable
bits : 6 - 6 (1 bit)

IC0ECCEN : ECC Icache0 Error Interrup Enable
bits : 8 - 8 (1 bit)

IC1ECCEN : ECC Icache1 Error Interrup Enable
bits : 9 - 9 (1 bit)

ICXIPECCEN : ECC IcacheXIP Error Interrup Enable
bits : 10 - 10 (1 bit)

FL0ECCEN : ECC Flash0 NError Interrup Enable
bits : 11 - 11 (1 bit)

FL1ECCEN : ECC Flash1 NError Interrup Enable
bits : 12 - 12 (1 bit)

DATARAMADDR : ECC Error Address.Data Ram Address.
bits : 0 - 12 (13 bit)

DATARAMBANK : ECC Error Address.Data Error Bank.
bits : 14 - 14 (1 bit)

DATARAMERR : ECC Error Address.Data Ram Error.
bits : 15 - 15 (1 bit)

TAGRAMADDR : ECC Error Address.Tag Ram Address.
bits : 16 - 28 (13 bit)

TAGRAMBANK : ECC Error Address.Tag Ram Bank.
bits : 30 - 30 (1 bit)

TAGRAMERR : ECC Error Address.Tag Ram Error.
bits : 31 - 31 (1 bit)

LDOWOEN : LDOWO Enable
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

LDOWOPULLD : LDOWO PULL Disable
bits : 1 - 1 (1 bit)

Enumeration:

End of enumeration elements list.

LDOWOVSEL : LDOWO Voltage Setting
bits : 2 - 3 (2 bit)

Enumeration:

End of enumeration elements list.

LDOWEN : LDOW Enable
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

LDOWPULLD : LDOW PULL Disable
bits : 5 - 5 (1 bit)

Enumeration:

End of enumeration elements list.

LDOWVSEL : LDOW Voltage Setting
bits : 6 - 7 (2 bit)

Enumeration:

End of enumeration elements list.

LDOBYP : LDO Bypass Enable
bits : 8 - 8 (1 bit)

Enumeration:

End of enumeration elements list.

LDOWDISCH : LDOW Discharge
bits : 9 - 9 (1 bit)

Enumeration:

End of enumeration elements list.

LDOWOENDLY : LDOWO Enable Delay Status
bits : 12 - 12 (1 bit)

Enumeration:

End of enumeration elements list.

LDOWENDLY : LDOW Enable Delay Status
bits : 13 - 13 (1 bit)

Enumeration:

End of enumeration elements list.

BYPDLYCNT : Bypass Delay Count. Count delay base on PCLK.
bits : 0 - 7 (8 bit)

LDOWDLYCNT : LDOW Delay Count. Count delay base on PCLK/128.
bits : 8 - 16 (9 bit)

LDOWODLYCNT : LDOWO Delay Count. Count delay base on PCLK/128.
bits : 20 - 28 (9 bit)

PSC : Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.
bits : 6 - 8 (3 bit)

Enumeration:

End of enumeration elements list.

CLKSEL : Clock Source Select. This 3 bit field selects the source for the system clock.
bits : 9 - 11 (3 bit)

Enumeration:

End of enumeration elements list.

CKRDY : Clock Ready. This read only bit reflects whether the currently selected system clock source is running.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CCD : Cryptographic clock divider
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

X32M_EN : 32MHz Crystal Oscillator Enable.
bits : 16 - 16 (1 bit)

Enumeration:

End of enumeration elements list.

X32K_EN : 32kHz Crystal Oscillator Enable.
bits : 17 - 17 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC_EN : 60MHz High Frequency Internal Reference Clock Enable.
bits : 18 - 18 (1 bit)

HIRC96M_EN : 96MHz High Frequency Internal Reference Clock Enable.
bits : 19 - 19 (1 bit)

HIRC8M_EN : 8MHz High Frequency Internal Reference Clock Enable.
bits : 20 - 20 (1 bit)

HIRC8M_VS : 8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M.
bits : 21 - 21 (1 bit)

Enumeration:

End of enumeration elements list.

X32M_RDY : 32MHz Crystal Oscillator Ready
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

X32K_RDY : 32kHz Crystal Oscillator Ready
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRC_RDY : 60MHz HIRC Ready.
bits : 26 - 26 (1 bit)

HIRC96M_RDY : 96MHz HIRC Ready.
bits : 27 - 27 (1 bit)

HIRC8M_RDY : 8MHz HIRC Ready.
bits : 28 - 28 (1 bit)

LIRC8K_RDY : 8kHz Low Frequency Reference Clock Ready.
bits : 29 - 29 (1 bit)

LIRC6K_RDY : 6kHz Low Frequency Reference Clock Ready.
bits : 30 - 30 (1 bit)

APBASYNCI2C0 : Feeds I2C0 with either PCLK or 7.37MHz Clk
bits : 0 - 0 (1 bit)

Enumeration:

End of enumeration elements list.

APBASYNCI2C1 : Feeds I2C1 with either PCLK or 7.37MHz Clk
bits : 1 - 1 (1 bit)

APBASYNCI2C2 : Feeds I2C2 with either PCLK or 7.37MHz Clk
bits : 2 - 2 (1 bit)

APBASYNCPT : Feeds PT with either PCLK or 7.37MHz Clk
bits : 3 - 3 (1 bit)

MODE : Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.
bits : 0 - 2 (3 bit)

Enumeration:

End of enumeration elements list.

GPIOWKEN : GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.
bits : 4 - 4 (1 bit)

Enumeration:

End of enumeration elements list.

RTCWKEN : RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.
bits : 5 - 5 (1 bit)

USBWKEN : USB Wake Up Enable. This bit enables USB activity as wakeup source.
bits : 6 - 6 (1 bit)

WUTWKEN : WUT Wake Up Enable. This bit enables WUT IRQ as wakeup source.
bits : 7 - 7 (1 bit)

SDMAWKEN : SDMA Wake Up Enable. This bit enables SDMA IRQ activity as wakeup source.
bits : 8 - 8 (1 bit)

HIRCPD : HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode.
bits : 15 - 15 (1 bit)

Enumeration:

End of enumeration elements list.

HIRC96MPD : 96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode.
bits : 16 - 16 (1 bit)

HIRC8MPD : 8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode.
bits : 17 - 17 (1 bit)