Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFF byte (0x0)
mem_usage : registers
protection : not protected
HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HTimer Control Register.
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HTEN : HTimer Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
ADE : Long Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
ASE : Short Interval Alarm Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.
bits : 2 - 2 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
BUSY : HTimer Busy. This bit is set to 1 by hardware when changes to HTimer registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : idle
Idle.
1 : busy
Busy.
End of enumeration elements list.
RDY : HTimer Ready. This bit is set to 1 by hardware when the HTimer count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the HTimer count register.
bits : 4 - 4 (1 bit)
Enumeration:
0 : busy
Register has not updated.
1 : ready
Ready.
End of enumeration elements list.
RDYE : HTimer Ready Interrupt Enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : dis
Disable.
1 : en
Enable.
End of enumeration elements list.
ALDF : Long Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : inactive
Not active
1 : pending
Active
End of enumeration elements list.
ALSF : Short Interval Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : inactive
Not active
1 : Pending
Active
End of enumeration elements list.
ACRE : Asynchronous Counter Read Enable, allows direct read access to sec and ssec counters regardless of the ready flag.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : disabled
Not allowed
1 : enabled
Allowed
End of enumeration elements list.
WE : Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical HTimer bits.
bits : 15 - 15 (1 bit)
Enumeration:
0 : dis
Not active
1 : en
Active
End of enumeration elements list.
HTimer Short Interval Counter. This counter ticks ever t_htclk (16.48uS). HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00.
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RTSS : HTimer Short Interval Counter.
bits : 0 - 7 (8 bit)
Long Interval Alarm.
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RAS : HTimer Long Interval Alarm. An Alarm is triggered when this value matches HTIMER_SEC[19:0]
bits : 0 - 19 (20 bit)
HTimer Short Interval Alarm. This register contains the reload value for the short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover.
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSSA : This register contains the reload value for the short interval alarm.
bits : 0 - 31 (32 bit)
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