\n

Pulse Train

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ENABLE

SAFE_EN

SAFE_DIS

RESYNC

INTFL

INTEN


ENABLE

Global Enable/Disable Controls for All Pulse Trains
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLE ENABLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt10 pt11 pt12 pt13 pt14 pt15

pt0 : Enable/Disable control for PT0
bits : 0 - 0 (1 bit)
access : read-write

pt1 : Enable/Disable control for PT1
bits : 1 - 1 (1 bit)
access : read-write

pt2 : Enable/Disable control for PT2
bits : 2 - 2 (1 bit)
access : read-write

pt3 : Enable/Disable control for PT3
bits : 3 - 3 (1 bit)
access : read-write

pt4 : Enable/Disable control for PT4
bits : 4 - 4 (1 bit)
access : read-write

pt5 : Enable/Disable control for PT5
bits : 5 - 5 (1 bit)
access : read-write

pt6 : Enable/Disable control for PT6
bits : 6 - 6 (1 bit)
access : read-write

pt7 : Enable/Disable control for PT7
bits : 7 - 7 (1 bit)
access : read-write

pt8 : Enable/Disable control for PT8
bits : 8 - 8 (1 bit)
access : read-write

pt9 : Enable/Disable control for PT9
bits : 9 - 9 (1 bit)
access : read-write

pt10 : Enable/Disable control for PT10
bits : 10 - 10 (1 bit)
access : read-write

pt11 : Enable/Disable control for PT11
bits : 11 - 11 (1 bit)
access : read-write

pt12 : Enable/Disable control for PT12
bits : 12 - 12 (1 bit)
access : read-write

pt13 : Enable/Disable control for PT13
bits : 13 - 13 (1 bit)
access : read-write

pt14 : Enable/Disable control for PT14
bits : 14 - 14 (1 bit)
access : read-write

pt15 : Enable/Disable control for PT15
bits : 15 - 15 (1 bit)
access : read-write


SAFE_EN

Pulse Train Global Safe Enable.
address_offset : 0x10 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SAFE_EN SAFE_EN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 PT10 PT11 PT12 PT13 PT14 PT15

PT0 :
bits : 0 - 0 (1 bit)
access : write-only

PT1 :
bits : 1 - 1 (1 bit)
access : write-only

PT2 :
bits : 2 - 2 (1 bit)
access : write-only

PT3 :
bits : 3 - 3 (1 bit)
access : write-only

PT4 :
bits : 4 - 4 (1 bit)
access : write-only

PT5 :
bits : 5 - 5 (1 bit)
access : write-only

PT6 :
bits : 6 - 6 (1 bit)
access : write-only

PT7 :
bits : 7 - 7 (1 bit)
access : write-only

PT8 :
bits : 8 - 8 (1 bit)
access : write-only

PT9 :
bits : 9 - 9 (1 bit)
access : write-only

PT10 :
bits : 10 - 10 (1 bit)
access : write-only

PT11 :
bits : 11 - 11 (1 bit)
access : write-only

PT12 :
bits : 12 - 12 (1 bit)
access : write-only

PT13 :
bits : 13 - 13 (1 bit)
access : write-only

PT14 :
bits : 14 - 14 (1 bit)
access : write-only

PT15 :
bits : 15 - 15 (1 bit)
access : write-only


SAFE_DIS

Pulse Train Global Safe Disable.
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SAFE_DIS SAFE_DIS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PT8 PT9 PT10 PT11 PT12 PT13 PT14 PT15

PT0 :
bits : 0 - 0 (1 bit)
access : write-only

PT1 :
bits : 1 - 1 (1 bit)
access : write-only

PT2 :
bits : 2 - 2 (1 bit)
access : write-only

PT3 :
bits : 3 - 3 (1 bit)
access : write-only

PT4 :
bits : 4 - 4 (1 bit)
access : write-only

PT5 :
bits : 5 - 5 (1 bit)
access : write-only

PT6 :
bits : 6 - 6 (1 bit)
access : write-only

PT7 :
bits : 7 - 7 (1 bit)
access : write-only

PT8 :
bits : 8 - 8 (1 bit)
access : write-only

PT9 :
bits : 9 - 9 (1 bit)
access : write-only

PT10 :
bits : 10 - 10 (1 bit)
access : write-only

PT11 :
bits : 11 - 11 (1 bit)
access : write-only

PT12 :
bits : 12 - 12 (1 bit)
access : write-only

PT13 :
bits : 13 - 13 (1 bit)
access : write-only

PT14 :
bits : 14 - 14 (1 bit)
access : write-only

PT15 :
bits : 15 - 15 (1 bit)
access : write-only


RESYNC

Global Resync (All Pulse Trains) Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESYNC RESYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt10 pt11 pt12 pt13 pt14 pt15

pt0 : Resync control for PT0
bits : 0 - 0 (1 bit)
access : read-write

pt1 : Resync control for PT1
bits : 1 - 1 (1 bit)
access : read-write

pt2 : Resync control for PT2
bits : 2 - 2 (1 bit)
access : read-write

pt3 : Resync control for PT3
bits : 3 - 3 (1 bit)
access : read-write

pt4 : Resync control for PT4
bits : 4 - 4 (1 bit)
access : read-write

pt5 : Resync control for PT5
bits : 5 - 5 (1 bit)
access : read-write

pt6 : Resync control for PT6
bits : 6 - 6 (1 bit)
access : read-write

pt7 : Resync control for PT7
bits : 7 - 7 (1 bit)
access : read-write

pt8 : Resync control for PT8
bits : 8 - 8 (1 bit)
access : read-write

pt9 : Resync control for PT9
bits : 9 - 9 (1 bit)
access : read-write

pt10 : Resync control for PT10
bits : 10 - 10 (1 bit)
access : read-write

pt11 : Resync control for PT11
bits : 11 - 11 (1 bit)
access : read-write

pt12 : Resync control for PT12
bits : 12 - 12 (1 bit)
access : read-write

pt13 : Resync control for PT13
bits : 13 - 13 (1 bit)
access : read-write

pt14 : Resync control for PT14
bits : 14 - 14 (1 bit)
access : read-write

pt15 : Resync control for PT15
bits : 15 - 15 (1 bit)
access : read-write


INTFL

Pulse Train Interrupt Flags
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFL INTFL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt10 pt11 pt12 pt13 pt14 pt15

pt0 : Pulse Train 0 Stopped Interrupt Flag
bits : 0 - 0 (1 bit)
access : read-write

pt1 : Pulse Train 1 Stopped Interrupt Flag
bits : 1 - 1 (1 bit)
access : read-write

pt2 : Pulse Train 2 Stopped Interrupt Flag
bits : 2 - 2 (1 bit)
access : read-write

pt3 : Pulse Train 3 Stopped Interrupt Flag
bits : 3 - 3 (1 bit)
access : read-write

pt4 : Pulse Train 4 Stopped Interrupt Flag
bits : 4 - 4 (1 bit)
access : read-write

pt5 : Pulse Train 5 Stopped Interrupt Flag
bits : 5 - 5 (1 bit)
access : read-write

pt6 : Pulse Train 6 Stopped Interrupt Flag
bits : 6 - 6 (1 bit)
access : read-write

pt7 : Pulse Train 7 Stopped Interrupt Flag
bits : 7 - 7 (1 bit)
access : read-write

pt8 : Pulse Train 8 Stopped Interrupt Flag
bits : 8 - 8 (1 bit)
access : read-write

pt9 : Pulse Train 9 Stopped Interrupt Flag
bits : 9 - 9 (1 bit)
access : read-write

pt10 : Pulse Train 10 Stopped Interrupt Flag
bits : 10 - 10 (1 bit)
access : read-write

pt11 : Pulse Train 11 Stopped Interrupt Flag
bits : 11 - 11 (1 bit)
access : read-write

pt12 : Pulse Train 12 Stopped Interrupt Flag
bits : 12 - 12 (1 bit)
access : read-write

pt13 : Pulse Train 13 Stopped Interrupt Flag
bits : 13 - 13 (1 bit)
access : read-write

pt14 : Pulse Train 14 Stopped Interrupt Flag
bits : 14 - 14 (1 bit)
access : read-write

pt15 : Pulse Train 15 Stopped Interrupt Flag
bits : 15 - 15 (1 bit)
access : read-write


INTEN

Pulse Train Interrupt Enable/Disable
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTEN INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pt0 pt1 pt2 pt3 pt4 pt5 pt6 pt7 pt8 pt9 pt10 pt11 pt12 pt13 pt14 pt15

pt0 : Pulse Train 0 Stopped Interrupt Enable/Disable
bits : 0 - 0 (1 bit)
access : read-write

pt1 : Pulse Train 1 Stopped Interrupt Enable/Disable
bits : 1 - 1 (1 bit)
access : read-write

pt2 : Pulse Train 2 Stopped Interrupt Enable/Disable
bits : 2 - 2 (1 bit)
access : read-write

pt3 : Pulse Train 3 Stopped Interrupt Enable/Disable
bits : 3 - 3 (1 bit)
access : read-write

pt4 : Pulse Train 4 Stopped Interrupt Enable/Disable
bits : 4 - 4 (1 bit)
access : read-write

pt5 : Pulse Train 5 Stopped Interrupt Enable/Disable
bits : 5 - 5 (1 bit)
access : read-write

pt6 : Pulse Train 6 Stopped Interrupt Enable/Disable
bits : 6 - 6 (1 bit)
access : read-write

pt7 : Pulse Train 7 Stopped Interrupt Enable/Disable
bits : 7 - 7 (1 bit)
access : read-write

pt8 : Pulse Train 8 Stopped Interrupt Enable/Disable
bits : 8 - 8 (1 bit)
access : read-write

pt9 : Pulse Train 9 Stopped Interrupt Enable/Disable
bits : 9 - 9 (1 bit)
access : read-write

pt10 : Pulse Train 10 Stopped Interrupt Enable/Disable
bits : 10 - 10 (1 bit)
access : read-write

pt11 : Pulse Train 11 Stopped Interrupt Enable/Disable
bits : 11 - 11 (1 bit)
access : read-write

pt12 : Pulse Train 12 Stopped Interrupt Enable/Disable
bits : 12 - 12 (1 bit)
access : read-write

pt13 : Pulse Train 13 Stopped Interrupt Enable/Disable
bits : 13 - 13 (1 bit)
access : read-write

pt14 : Pulse Train 14 Stopped Interrupt Enable/Disable
bits : 14 - 14 (1 bit)
access : read-write

pt15 : Pulse Train 15 Stopped Interrupt Enable/Disable
bits : 15 - 15 (1 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.