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Pulse Train

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RATE_LENGTH

TRAIN

LOOP

RESTART


RATE_LENGTH

Pulse Train Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RATE_LENGTH RATE_LENGTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rate_control mode

rate_control : Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.
bits : 0 - 26 (27 bit)
access : read-write

mode : Pulse Train Output Mode/Train Length
bits : 27 - 31 (5 bit)
access : read-write

Enumeration:

0 : 32_BIT

Pulse train, 32 bit pattern.

1 : SQUARE_WAVE

Square wave mode.

2 : 2_BIT

Pulse train, 2 bit pattern.

3 : 3_BIT

Pulse train, 3 bit pattern.

4 : 4_BIT

Pulse train, 4 bit pattern.

5 : 5_BIT

Pulse train, 5 bit pattern.

6 : 6_BIT

Pulse train, 6 bit pattern.

7 : 7_BIT

Pulse train, 7 bit pattern.

8 : 8_BIT

Pulse train, 8 bit pattern.

9 : 9_BIT

Pulse train, 9 bit pattern.

10 : 10_BIT

Pulse train, 10 bit pattern.

11 : 11_BIT

Pulse train, 11 bit pattern.

12 : 12_BIT

Pulse train, 12 bit pattern.

13 : 13_BIT

Pulse train, 13 bit pattern.

14 : 14_BIT

Pulse train, 14 bit pattern.

15 : 15_BIT

Pulse train, 15 bit pattern.

16 : 16_BIT

Pulse train, 16 bit pattern.

17 : 17_BIT

Pulse train, 17 bit pattern.

18 : 18_BIT

Pulse train, 18 bit pattern.

19 : 19_BIT

Pulse train, 19 bit pattern.

20 : 20_BIT

Pulse train, 20 bit pattern.

21 : 21_BIT

Pulse train, 21 bit pattern.

22 : 22_BIT

Pulse train, 22 bit pattern.

23 : 23_BIT

Pulse train, 23 bit pattern.

24 : 24_BIT

Pulse train, 24 bit pattern.

25 : 25_BIT

Pulse train, 25 bit pattern.

26 : 26_BIT

Pulse train, 26 bit pattern.

27 : 27_BIT

Pulse train, 27 bit pattern.

28 : 28_BIT

Pulse train, 28 bit pattern.

29 : 29_BIT

Pulse train, 29 bit pattern.

30 : 30_BIT

Pulse train, 30 bit pattern.

31 : 31_BIT

Pulse train, 31 bit pattern.

End of enumeration elements list.


TRAIN

Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRAIN TRAIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LOOP

Pulse Train Loop Count
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOOP LOOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 count delay

count : Number of loops for this pulse train to repeat.
bits : 0 - 15 (16 bit)
access : read-write

delay : Delay between loops of the Pulse Train in PT Peripheral Clock cycles
bits : 16 - 27 (12 bit)
access : read-write


RESTART

Pulse Train Auto-Restart Configuration.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESTART RESTART read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pt_x_select on_pt_x_loop_exit pt_y_select on_pt_y_loop_exit

pt_x_select : Auto-Restart PT X Select
bits : 0 - 4 (5 bit)
access : read-write

on_pt_x_loop_exit : Enable Auto-Restart on PT X Loop Exit
bits : 7 - 7 (1 bit)
access : read-write

pt_y_select : Auto-Restart PT Y Select
bits : 8 - 12 (5 bit)
access : read-write

on_pt_y_loop_exit : Enable Auto-Restart on PT Y Loop Exit
bits : 15 - 15 (1 bit)
access : read-write



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