Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Low Power Control Register.
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RAMRET : System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit.
bits : 0 - 1 (2 bit)
Enumeration:
0 : dis
Disable Ram Retention.
1 : en1
Enable System RAM 0 retention.
2 : en2
Enable System RAM 0 and 1 retention.
3 : en3
Enable System RAM 0 and 1 retention, if RREGEN=0, Enable all System RAM retention.
End of enumeration elements list.
OVR : Operating Voltage Range
bits : 4 - 5 (2 bit)
Enumeration:
0 : 0_9V
0.9V 24MHz
1 : 1_0V
1.0V 48MHz
2 : 1_1V
1.1V 96MHz
End of enumeration elements list.
BLKDET : Block Auto-Detect
bits : 6 - 6 (1 bit)
Enumeration:
0 : enabled
enable
1 : Disable
disable
End of enumeration elements list.
FVDDEN : Flash VDD Enabled
bits : 7 - 7 (1 bit)
RREGEN : Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode.
bits : 8 - 8 (1 bit)
Enumeration:
0 : dis
Disabled.
1 : en
Enabled.
End of enumeration elements list.
BCKGRND : Background Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep.
bits : 9 - 9 (1 bit)
Enumeration:
0 : dis
Disabled.
1 : en
Enabled.
End of enumeration elements list.
FWKM : Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical).
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Disabled.
1 : en
Enabled.
End of enumeration elements list.
BGOFF : Bandgap OFF. This controls the System Bandgap in DeepSleep mode.
bits : 11 - 11 (1 bit)
Enumeration:
0 : on
Bandgap is always ON.
1 : off
Bandgap is OFF in DeepSleep mode(default).
End of enumeration elements list.
PORVDDCMD : VDDC(VCore) Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode.
bits : 12 - 12 (1 bit)
Enumeration:
0 : dis
Disabled.
1 : en
Enabled.
End of enumeration elements list.
VDDCMD : VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.
bits : 20 - 20 (1 bit)
Enumeration:
0 : en
Enable if Bandgap is ON(default)
1 : dis
Disabled.
End of enumeration elements list.
VRTCMD : VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes.
bits : 21 - 21 (1 bit)
Enumeration:
0 : en
Enable if Bandgap is ON(default)
1 : dis
Disabled.
End of enumeration elements list.
VDDAMD : VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.
bits : 22 - 22 (1 bit)
Enumeration:
0 : en
Enable if Bandgap is ON(default)
1 : dis
Disabled.
End of enumeration elements list.
VDDIOMD : VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.
bits : 23 - 23 (1 bit)
Enumeration:
0 : en
Enable if Bandgap is ON(default)
1 : dis
Disabled.
End of enumeration elements list.
VDDIOHMD : VFDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.
bits : 24 - 24 (1 bit)
Enumeration:
0 : en
Enable if Bandgap is ON(default)
1 : dis
Disabled.
End of enumeration elements list.
PORVDDIOMD : VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.
bits : 25 - 25 (1 bit)
Enumeration:
0 : dis
Disabled.
1 : en
Enabled.
End of enumeration elements list.
PORVDDIOHMD : VDDIOH Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIOH supply in all operating mods.
bits : 26 - 26 (1 bit)
Enumeration:
0 : dis
Disabled.
1 : en
Enabled.
End of enumeration elements list.
VDDBMD : VDDB Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods.
bits : 27 - 27 (1 bit)
Enumeration:
0 : dis
Disabled.
1 : en
Enabled.
End of enumeration elements list.
Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power Peripheral Wakeup Status Register.
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBLSWKST : USB UTMI Linestate Detect Wakeup Flag(write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN.
bits : 0 - 1 (2 bit)
USBVBUSWKST : USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off.
bits : 2 - 2 (1 bit)
SDMAWKST : Smart DMA Detect Wakeup Flag (write one to clear). This bit will be set when the SDMA IRQ transition from low to high or on high to low.
bits : 3 - 3 (1 bit)
BBMODEST : Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.
bits : 16 - 16 (1 bit)
Low Power Peripheral Wakeup Enable Register.
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBLSWKEN : USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set.
bits : 0 - 1 (2 bit)
USBVBUSWKEN : USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.
bits : 2 - 2 (1 bit)
SDMAWKEN : Smart DMA Wakeup Enable. This bit allows wakeup from the Smart DMA IRQ.
bits : 3 - 3 (1 bit)
Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEST : Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.
bits : 0 - 0 (1 bit)
Low Power Memory Shutdown Control.
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRAM0SD : System RAM block 0 Shut Down.
bits : 0 - 0 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
SRAM1SD : System RAM block 1 Shut Down.
bits : 1 - 1 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
SRAM2SD : System RAM block 2 Shut Down.
bits : 2 - 2 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
SRAM3SD : System RAM block 3 Shut Down.
bits : 3 - 3 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
SRAM4SD : System RAM block 4 Shut Down.
bits : 4 - 4 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
SRAM5SD : System RAM block 5 Shut Down.
bits : 5 - 5 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
SRAM6SD : System RAM block 6 Shut Down.
bits : 6 - 6 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
ICACHESD : Instruction Cache RAM Shut Down.
bits : 7 - 7 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
ICACHEXIPSD : XiP Instruction Cache RAM Shut Down.
bits : 8 - 8 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
SCACHESD : System Cache RAM Shut Down.
bits : 9 - 9 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
CRYPTOSD : Crypto MAA RAM Shut Down.
bits : 10 - 10 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
USBFIFOSD : USB FIFO Shut Down.
bits : 11 - 11 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
ROMSD : ROM Shut Down.
bits : 12 - 12 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
ROM1SD : ROM1 Shut Down.
bits : 13 - 13 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
IC1SD : ICache 1 Shut Down.
bits : 14 - 14 (1 bit)
Enumeration:
0 : normal
Normal Operating Mode.
1 : shutdown
Shutdown Mode.
End of enumeration elements list.
Low Power VDD Domain Power Down Control.
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VREGOBPD : Power down SIMO Vreg B (VCOREB+VDDC) in backup mode.
bits : 0 - 0 (1 bit)
Enumeration:
0 : up
Enabled in backup mode.
1 : down
Disabled in backup mode.
End of enumeration elements list.
VREGODPD : Power down SIMO Vreg D (BTLE).
bits : 1 - 1 (1 bit)
Enumeration:
0 : up
Enabled
1 : down
Disabled
End of enumeration elements list.
VDD2PD : Power down VDD2 (CPU0+peripherals).
bits : 8 - 8 (1 bit)
Enumeration:
0 : up
Enabled
1 : down
Disabled
End of enumeration elements list.
VDD3PD : Power down VDD3 (CPU1+audio).
bits : 9 - 9 (1 bit)
Enumeration:
0 : up
Enabled
1 : down
Disabled
End of enumeration elements list.
VDD4PD : Power down VDD4 (SDMA+peripherals).
bits : 10 - 10 (1 bit)
Enumeration:
0 : up
Enabled
1 : down
Disabled
End of enumeration elements list.
VDD5PD : Power down VDD5 (BTLE digital).
bits : 11 - 11 (1 bit)
Enumeration:
0 : up
Enabled
1 : down
Disabled
End of enumeration elements list.
General Purpose Register 0
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
General Purpose Register 1
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power Multi-Core Status
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power Multi-Core Request
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEEN : Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.
bits : 0 - 30 (31 bit)
Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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