Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
GCR Protection Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the GCR
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the GCR
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the GCR
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the GCR
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the GCR
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the GCR
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the GCR
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the GCR
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the GCR
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
TMR0 Protection Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the TMR0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the TMR0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the TMR0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the TMR0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the TMR0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the TMR0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the TMR0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the TMR0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the TMR0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
TMR1 Protection Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the TMR1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the TMR1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the TMR1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the TMR1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the TMR1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the TMR1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the TMR1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the TMR1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the TMR1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
TMR2 Protection Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the TMR2
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the TMR2
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the TMR2
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the TMR2
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the TMR2
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the TMR2
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the TMR2
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the TMR2
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the TMR2
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
TMR3 Protection Register
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the TMR3
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the TMR3
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the TMR3
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the TMR3
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the TMR3
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the TMR3
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the TMR3
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the TMR3
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the TMR3
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
TMR4 Protection Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the TMR4
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the TMR4
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the TMR4
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the TMR4
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the TMR4
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the TMR4
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the TMR4
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the TMR4
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the TMR4
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
TMR5 Protection Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the TMR5
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the TMR5
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the TMR5
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the TMR5
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the TMR5
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the TMR5
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the TMR5
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the TMR5
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the TMR5
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
HTimer0 Protection Register
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the HTimer0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the HTimer0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the HTimer0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the HTimer0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the HTimer0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the HTimer0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the HTimer0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the HTimer0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the HTimer0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
HTimer1 Protection Register
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the HTimer1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the HTimer1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the HTimer1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the HTimer1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the HTimer1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the HTimer1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the HTimer1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the HTimer1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the HTimer1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
I2C0 Protection Register
address_offset : 0x1D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the I2C0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the I2C0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the I2C0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the I2C0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the I2C0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the I2C0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the I2C0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the I2C0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the I2C0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
I2C1 Protection Register
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the I2C1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the I2C1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the I2C1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the I2C1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the I2C1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the I2C1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the I2C1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the I2C1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the I2C1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
I2C2 Protection Register
address_offset : 0x1F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the I2C2
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the I2C2
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the I2C2
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the I2C2
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the I2C2
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the I2C2
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the I2C2
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the I2C2
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the I2C2
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SPI-XIP Master Protection Register
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the SPI-XIP Master
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the SPI-XIP Master
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the SPI-XIP Master
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the SPI-XIP Master
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the SPI-XIP Master
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the SPI-XIP Master
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the SPI-XIP Master
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the SPI-XIP Master
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the SPI-XIP Master
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SPI-XIP Master Controller Protection Register
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the SPI-XIP Master Controller
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the SPI-XIP Master Controller
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the SPI-XIP Master Controller
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the SPI-XIP Master Controller
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the SPI-XIP Master Controller
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the SPI-XIP Master Controller
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the SPI-XIP Master Controller
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the SPI-XIP Master Controller
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the SPI-XIP Master Controller
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0 Protection Register
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the DMA0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the DMA0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the DMA0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the DMA0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the DMA0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the DMA0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the DMA0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the DMA0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the DMA0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Flash 0 Protection Register
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Flash 0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Flash 0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Flash 0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Flash 0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Flash 0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Flash 0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Flash 0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Flash 0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Flash 0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Flash 1 Protection Register
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Flash 1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Flash 1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Flash 1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Flash 1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Flash 1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Flash 1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Flash 1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Flash 1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Flash 1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Instruction Cache 0 Protection Register
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Instruction Cache 0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Instruction Cache 0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Instruction Cache 0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Instruction Cache 0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Instruction Cache 0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Instruction Cache 0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Instruction Cache 0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Instruction Cache 0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Instruction Cache 0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Instruction Cache 1 Protection Register
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Instruction Cache 1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Instruction Cache 1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Instruction Cache 1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Instruction Cache 1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Instruction Cache 1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Instruction Cache 1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Instruction Cache 1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Instruction Cache 1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Instruction Cache 1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Instruction Cache XIP Protection Register
address_offset : 0x2F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Instruction Cache XIP
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Instruction Cache XIP
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Instruction Cache XIP
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Instruction Cache XIP
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Instruction Cache XIP
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Instruction Cache XIP
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Instruction Cache XIP
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Instruction Cache XIP
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Instruction Cache XIP
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Watchdog 0 Protection Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Watchdog 0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Watchdog 0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Watchdog 0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Watchdog 0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Watchdog 0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Watchdog 0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Watchdog 0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Watchdog 0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Watchdog 0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Data Cache Controller Protection Register
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Data Cache Controller
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Data Cache Controller
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Data Cache Controller
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Data Cache Controller
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Data Cache Controller
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Data Cache Controller
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Data Cache Controller
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Data Cache Controller
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Data Cache Controller
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Watchdog 1 Protection Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Watchdog 1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Watchdog 1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Watchdog 1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Watchdog 1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Watchdog 1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Watchdog 1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Watchdog 1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Watchdog 1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Watchdog 1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
ADC Protection Register
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the ADC
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the ADC
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the ADC
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the ADC
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the ADC
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the ADC
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the ADC
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the ADC
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the ADC
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1 Protection Register
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the DMA1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the DMA1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the DMA1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the DMA1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the DMA1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the DMA1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the DMA1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the DMA1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the DMA1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMA Protection Register
address_offset : 0x360 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the SDMA
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the SDMA
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the SDMA
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the SDMA
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the SDMA
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the SDMA
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the SDMA
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the SDMA
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the SDMA
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDHC Controller Protection Register
address_offset : 0x370 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the SDHC Controller
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the SDHC Controller
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the SDHC Controller
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the SDHC Controller
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the SDHC Controller
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the SDHC Controller
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the SDHC Controller
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the SDHC Controller
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the SDHC Controller
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Watchdog 2 Protection Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Watchdog 2
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Watchdog 2
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Watchdog 2
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Watchdog 2
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Watchdog 2
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Watchdog 2
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Watchdog 2
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Watchdog 2
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Watchdog 2
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SPI Data Controller Protection Register
address_offset : 0x3A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the SPI Data Controller
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the SPI Data Controller
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the SPI Data Controller
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the SPI Data Controller
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the SPI Data Controller
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the SPI Data Controller
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the SPI Data Controller
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the SPI Data Controller
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the SPID
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Pulse Train Protection Register
address_offset : 0x3C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Pulse Train
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Pulse Train
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Pulse Train
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Pulse Train
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Pulse Train
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Pulse Train
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Pulse Train
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Pulse Train
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Pulse Train
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
One Wire Master Protection Register
address_offset : 0x3D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the One Wire Master
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the One Wire Master
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the One Wire Master
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the One Wire Master
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the One Wire Master
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the One Wire Master
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the One Wire Master
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the One Wire Master
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the One Wire Master
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Semaphores Protection Register
address_offset : 0x3E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Semaphores
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Semaphores
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Semaphores
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Semaphores
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Semaphores
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Semaphores
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Semaphores
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Semaphores
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Semaphores
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SIR Protection Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the SIR
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the SIR
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the SIR
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the SIR
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the SIR
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the SIR
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the SIR
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the SIR
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the SIR
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SMON Protection Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the SMON
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the SMON
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the SMON
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the SMON
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the SMON
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the SMON
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the SMON
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the SMON
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the SMON
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
UART0 Protection Register
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the UART0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the UART0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the UART0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the UART0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the UART0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the UART0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the UART0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the UART0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the UART0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
UART1 Protection Register
address_offset : 0x430 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the UART1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the UART1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the UART1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the UART1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the UART1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the UART1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the UART1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the UART1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the UART1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SIMO Protection Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the SIMO
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the SIMO
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the SIMO
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the SIMO
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the SIMO
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the SIMO
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the SIMO
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the SIMO
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the SIMO
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
UART2 Protection Register
address_offset : 0x440 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the UART2
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the UART2
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the UART2
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the UART2
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the UART2
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the UART2
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the UART2
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the UART2
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the UART2
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
QSPI1 Protection Register
address_offset : 0x460 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the QSPI1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the QSPI1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the QSPI1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the QSPI1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the QSPI1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the QSPI1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the QSPI1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the QSPI1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the QSPI1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DVS Protection Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the DVS
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the DVS
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the DVS
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the DVS
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the DVS
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the DVS
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the DVS
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the DVS
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the DVS
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
QSPI2 Protection Register
address_offset : 0x480 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the QSPI2
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the QSPI2
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the QSPI2
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the QSPI2
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the QSPI2
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the QSPI2
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the QSPI2
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the QSPI2
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the QSPI2
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Audio Subsystem Protection Register
address_offset : 0x4C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Audio Subsystem
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Audio Subsystem
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Audio Subsystem
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Audio Subsystem
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Audio Subsystem
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Audio Subsystem
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Audio Subsystem
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Audio Subsystem
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Audio Subsystem
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
TRNG Protection Register
address_offset : 0x4D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the TRNG
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the TRNG
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the TRNG
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the TRNG
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the TRNG
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the TRNG
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the TRNG
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the TRNG
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the TRNG
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
BTLE Registers Protection Register
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the BTLE Registers
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the BTLE Registers
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the BTLE Registers
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the BTLE Registers
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the BTLE Registers
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the BTLE Registers
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the BTLE Registers
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the BTLE Registers
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the BTLE Registers
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
BBSIR Protection Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the BBSIR
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the BBSIR
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the BBSIR
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the BBSIR
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the BBSIR
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the BBSIR
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the BBSIR
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the BBSIR
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the BBSIR
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
RTC Protection Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the RTC
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the RTC
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the RTC
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the RTC
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the RTC
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the RTC
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the RTC
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the RTC
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the RTC
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Wakeup Timer Protection Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Wakeup Timer
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Wakeup Timer
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Wakeup Timer
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Wakeup Timer
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Wakeup Timer
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Wakeup Timer
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Wakeup Timer
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Wakeup Timer
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Wakeup Timer
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Power Sequencer Protection Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Power Sequencer
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Power Sequencer
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Power Sequencer
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Power Sequencer
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Power Sequencer
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Power Sequencer
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Power Sequencer
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Power Sequencer
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Power Sequencer
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
BBCR Protection Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the BBCR
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the BBCR
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the BBCR
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the BBCR
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the BBCR
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the BBCR
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the BBCR
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the BBCR
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the BBCR
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
FCR Protection Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the FCR
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the FCR
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the FCR
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the FCR
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the FCR
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the FCR
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the FCR
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the FCR
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the FCR
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
GPIO0 Protection Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the GPIO0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the GPIO0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the GPIO0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the GPIO0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the GPIO0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the GPIO0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the GPIO0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the GPIO0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the GPIO0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
GPIO1 Protection Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the GPIO1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the GPIO1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the GPIO1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the GPIO1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the GPIO1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the GPIO1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the GPIO1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the GPIO1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the GPIO1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBHS Protection Register
address_offset : 0xB10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the USBHS
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the USBHS
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the USBHS
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the USBHS
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the USBHS
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the USBHS
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the USBHS
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the USBHS
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the USBHS
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the USBHS
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the USBHS
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the USBHS
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the USBHS
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the USBHS
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the USBHS
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the USBHS
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the USBHS
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the USBHS
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIO Protection Register
address_offset : 0xB60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SDIO
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SDIO
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SDIO
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SDIO
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SDIO
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SDIO
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SDIO
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SDIO
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SDIO
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SDIO
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SDIO
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SDIO
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SDIO
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SDIO
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SDIO
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SDIO
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SDIO
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SDIO
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SPI XIP Master FIFO Protection Register
address_offset : 0xBC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SPI XIP Master FIFO
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SPI XIP Master FIFO
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SPI XIP Master FIFO
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SPI XIP Master FIFO
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SPI XIP Master FIFO
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SPI XIP Master FIFO
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SPI XIP Master FIFO
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SPI XIP Master FIFO
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SPI XIP Master FIFO
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SPI XIP Master FIFO
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SPI XIP Master FIFO
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SPI XIP Master FIFO
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SPI XIP Master FIFO
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SPI XIP Master FIFO
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SPI XIP Master FIFO
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SPI XIP Master FIFO
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SPI XIP Master FIFO
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SPI XIP Master FIFO
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
QSPI0 Protection Register
address_offset : 0xBE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the QSPI0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the QSPI0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the QSPI0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the QSPI0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the QSPI0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the QSPI0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the QSPI0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the QSPI0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the QSPI0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the QSPI0
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the QSPI0
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the QSPI0
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the QSPI0
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the QSPI0
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the QSPI0
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the QSPI0
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the QSPI0
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the QSPI0
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
Crypto Protection Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACN : Allow/Disallow DMA0 access to the Crypto
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACN : Allow/Disallow DMA1 access to the Crypto
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACN : Allow/Disallow USB access to the Crypto
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACN : Allow/Disallow SYS0 access to the Crypto
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACN : Allow/Disallow SYS1 access to the Crypto
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACN : Allow/Disallow SDMA Data access to the Crypto
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACN : Allow/Disallow SDMA Instruction access to the Crypto
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACN : Allow/Disallow CRYPTO access to the Crypto
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACN : Allow/Disallow SDIO access to the Crypto
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SRAM0 Protection Register
address_offset : 0xF00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SRAM0
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SRAM0
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SRAM0
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SRAM0
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SRAM0
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SRAM0
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SRAM0
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SRAM0
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SRAM0
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SRAM0
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SRAM0
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SRAM0
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SRAM0
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SRAM0
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SRAM0
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SRAM0
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SRAM0
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SRAM0
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SRAM1 Protection Register
address_offset : 0xF10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SRAM1
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SRAM1
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SRAM1
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SRAM1
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SRAM1
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SRAM1
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SRAM1
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SRAM1
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SRAM1
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SRAM1
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SRAM1
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SRAM1
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SRAM1
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SRAM1
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SRAM1
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SRAM1
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SRAM1
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SRAM1
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SRAM2 Protection Register
address_offset : 0xF20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SRAM2
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SRAM2
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SRAM2
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SRAM2
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SRAM2
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SRAM2
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SRAM2
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SRAM2
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SRAM2
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SRAM2
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SRAM2
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SRAM2
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SRAM2
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SRAM2
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SRAM2
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SRAM2
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SRAM2
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SRAM2
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SRAM3 Protection Register
address_offset : 0xF30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SRAM3
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SRAM3
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SRAM3
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SRAM3
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SRAM3
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SRAM3
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SRAM3
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SRAM3
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SRAM3
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SRAM3
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SRAM3
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SRAM3
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SRAM3
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SRAM3
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SRAM3
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SRAM3
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SRAM3
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SRAM3
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SRAM4 Protection Register
address_offset : 0xF40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SRAM4
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SRAM4
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SRAM4
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SRAM4
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SRAM4
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SRAM4
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SRAM4
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SRAM4
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SRAM4
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SRAM4
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SRAM4
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SRAM4
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SRAM4
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SRAM4
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SRAM4
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SRAM4
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SRAM4
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SRAM4
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SRAM5 Protection Register
address_offset : 0xF50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SRAM5
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SRAM5
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SRAM5
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SRAM5
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SRAM5
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SRAM5
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SRAM5
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SRAM5
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SRAM5
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SRAM5
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SRAM5
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SRAM5
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SRAM5
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SRAM5
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SRAM5
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SRAM5
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SRAM5
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SRAM5
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SRAM6 Protection Register
address_offset : 0xF60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0ACNR : Allow/Disallow DMA0 Read access to the SRAM6
bits : 0 - 0 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA0ACNW : Allow/Disallow DMA0 Write access to the SRAM6
bits : 1 - 1 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNR : Allow/Disallow DMA1 Read access to the SRAM6
bits : 2 - 2 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
DMA1ACNW : Allow/Disallow DMA1 Write access to the SRAM6
bits : 3 - 3 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNR : Allow/Disallow USB Read access to the SRAM6
bits : 4 - 4 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
USBACNW : Allow/Disallow USB Write access to the SRAM6
bits : 5 - 5 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNR : Allow/Disallow SYS0 Read access to the SRAM6
bits : 6 - 6 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS0ACNW : Allow/Disallow SYS0 Write access to the SRAM6
bits : 7 - 7 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNR : Allow/Disallow SYS1 Read access to the SRAM6
bits : 8 - 8 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SYS1ACNW : Allow/Disallow SYS1 Write access to the SRAM6
bits : 9 - 9 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNR : Allow/Disallow SDMA Data Read access to the SRAM6
bits : 10 - 10 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMADACNW : Allow/Disallow SDMA Data Write access to the SRAM6
bits : 11 - 11 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNR : Allow/Disallow SDMA Instruction Read access to the SRAM6
bits : 12 - 12 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDMAIACNW : Allow/Disallow SDMA Instruction Write access to the SRAM6
bits : 13 - 13 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNR : Allow/Disallow CRYPTO Read access to the SRAM6
bits : 14 - 14 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
CRYPTOACNW : Allow/Disallow CRYPTO Write access to the SRAM6
bits : 15 - 15 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNR : Allow/Disallow SDIO Read access to the SRAM6
bits : 16 - 16 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
SDIOACNW : Allow/Disallow SDIO Write access to the SRAM6
bits : 17 - 17 (1 bit)
Enumeration:
1 : dis
Disallow
0 : allow
Allow
End of enumeration elements list.
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