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SDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IP

BP

OFFS

LC0

LC1

A0

A1

A2

A3

WDCN

SP

DP0

INT_MUX_CTRL0

INT_MUX_CTRL1

INT_MUX_CTRL2

INT_MUX_CTRL3

IP_ADDR

CTRL

INT_IN_CTRL

INT_IN_FLAG

INT_IN_IE

IRQ_FLAG

IRQ_IE

DP1


IP

Q30E Instruction Pointer.
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IP IP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BP

Q30E Frame Pointer Base.
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BP BP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OFFS

Q30E Frame Pointer Offset.
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OFFS OFFS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LC0

Q30E Loop Counter 0.
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LC0 LC0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LC1

Q30E Loop Counter 1.
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

LC1 LC1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A0

Q30E Accumulator 0.
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

A0 A0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A1

Q30E Accumulator 1.
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

A1 A1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A2

Q30E Accumulator 2.
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

A2 A2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

A3

Q30E Accumulator 3.
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

A3 A3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

WDCN

Q30E Watchdog Control.
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WDCN WDCN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SP

Q30E Stack Pointer.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SP SP read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DP0

Q30E Data Pointer 0.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DP0 DP0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

INT_MUX_CTRL0

Interrupt Mux Control 0.
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MUX_CTRL0 INT_MUX_CTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL16 INTSEL17 INTSEL18 INTSEL19

INTSEL16 : Interrupt Selection For 16th Interrupt.
bits : 0 - 7 (8 bit)

INTSEL17 : Interrupt Selection For 17th Interrupt.
bits : 8 - 15 (8 bit)

INTSEL18 : Interrupt Selection For 18th Interrupt.
bits : 16 - 23 (8 bit)

INTSEL19 : Interrupt Selection For 19th Interrupt.
bits : 24 - 31 (8 bit)


INT_MUX_CTRL1

Interrupt Mux Control 1.
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MUX_CTRL1 INT_MUX_CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL20 INTSEL21 INTSEL22 INTSEL23

INTSEL20 : Interrupt Selection For 20th Interrupt.
bits : 0 - 7 (8 bit)

INTSEL21 : Interrupt Selection For 21st Interrupt.
bits : 8 - 15 (8 bit)

INTSEL22 : Interrupt Selection For 22nd Interrupt.
bits : 16 - 23 (8 bit)

INTSEL23 : Interrupt Selection For 23rd Interrupt.
bits : 24 - 31 (8 bit)


INT_MUX_CTRL2

Interrupt Mux Control 2.
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MUX_CTRL2 INT_MUX_CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL24 INTSEL25 INTSEL26 INTSEL27

INTSEL24 : Interrupt Selection For 24th Interrupt.
bits : 0 - 7 (8 bit)

INTSEL25 : Interrupt Selection For 25th Interrupt.
bits : 8 - 15 (8 bit)

INTSEL26 : Interrupt Selection For 26th Interrupt.
bits : 16 - 23 (8 bit)

INTSEL27 : Interrupt Selection For 27th Interrupt.
bits : 24 - 31 (8 bit)


INT_MUX_CTRL3

Interrupt Mux Control 3.
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_MUX_CTRL3 INT_MUX_CTRL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSEL28 INTSEL29 INTSEL30 INTSEL31

INTSEL28 : Interrupt Selection For 28th Interrupt.
bits : 0 - 7 (8 bit)

INTSEL29 : Interrupt Selection For 29th Interrupt.
bits : 8 - 15 (8 bit)

INTSEL30 : Interrupt Selection For 30th Interrupt.
bits : 16 - 23 (8 bit)

INTSEL31 : Interrupt Selection For 31st Interrupt.
bits : 24 - 31 (8 bit)


IP_ADDR

Configurable starting IP address for Q30E.
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IP_ADDR IP_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_IP_ADDR

START_IP_ADDR : Starting IP address for Q30E
bits : 0 - 31 (32 bit)


CTRL

Control Register.
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : Enable SDMA.
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

Disable SDMA.

1 : en

Enable SDMA.

End of enumeration elements list.


INT_IN_CTRL

Interrupt Input From CPU Control Register.
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_IN_CTRL INT_IN_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSET

INTSET : Set Interrupt Flag.
bits : 0 - 0 (1 bit)

Enumeration:

0 : dis

Set interrupt Flag to 0.

1 : set

Set Interrupt Flag to 1.

End of enumeration elements list.


INT_IN_FLAG

Interrupt Input From CPU Flag.
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_IN_FLAG INT_IN_FLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTFLAG

INTFLAG : Interrupt Flag.
bits : 0 - 0 (1 bit)

Enumeration:

0 : no_eff

No Effect.

1 : clear

INT_IN_FLAG =0

End of enumeration elements list.


INT_IN_IE

Interrupt Input From CPU Enable.
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_IN_IE INT_IN_IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_IN_EN

INT_IN_EN : Interrupt Enable.
bits : 0 - 0 (1 bit)


IRQ_FLAG

Interrupt Output To CPU Flag.
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_FLAG IRQ_FLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ_FLAG

IRQ_FLAG : Interrupt Flag.
bits : 0 - 0 (1 bit)


IRQ_IE

Interrupt Output To CPU Control Register.
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_IE IRQ_IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ_EN

IRQ_EN : Interrupt Enable.
bits : 0 - 0 (1 bit)


DP1

Q30E Data Pointer 1.
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DP1 DP1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


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