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SIMO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

VREGO_D

IPKA

IPKB

MAXTON

ILOAD_A

ILOAD_B

ILOAD_C

ILOAD_D

BUCK_ALERT_THR_A

BUCK_ALERT_THR_B

BUCK_ALERT_THR_C

BUCK_ALERT_THR_D

VREGO_A

BUCK_OUT_READY

ZERO_CROSS_CAL_A

ZERO_CROSS_CAL_B

ZERO_CROSS_CAL_C

ZERO_CROSS_CAL_D

VREGO_B

VREGO_C


VREGO_D

Buck Voltage Regulator D Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREGO_D VREGO_D read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSETD RANGED

VSETD : Regulator Output Voltage Setting
bits : 0 - 6 (7 bit)

RANGED : Regulator Output Range Set
bits : 7 - 7 (1 bit)

Enumeration:

0 : low

Low output voltage range

1 : high

High output voltage range

End of enumeration elements list.


IPKA

High Side FET Peak Current VREGO_A/VREGO_B Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPKA IPKA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPKSETA IPKSETB

IPKSETA : Voltage Regulator Peak Current Setting
bits : 0 - 3 (4 bit)

IPKSETB : Voltage Regulator Peak Current Setting
bits : 4 - 7 (4 bit)


IPKB

High Side FET Peak Current VREGO_C/VREGO_D Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IPKB IPKB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPKSETC IPKSETD

IPKSETC : Voltage Regulator Peak Current Setting
bits : 0 - 3 (4 bit)

IPKSETD : Voltage Regulator Peak Current Setting
bits : 4 - 7 (4 bit)


MAXTON

Maximum High Side FET Time On Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAXTON MAXTON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TONSET

TONSET : Sets the maximum on time for the high side FET, each increment represents 500ns
bits : 0 - 3 (4 bit)


ILOAD_A

Buck Cycle Count VREGO_A Register
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ILOAD_A ILOAD_A read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ILOADA

ILOADA : Number of buck cycles that occur within the cycle clock
bits : 0 - 7 (8 bit)


ILOAD_B

Buck Cycle Count VREGO_B Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ILOAD_B ILOAD_B read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ILOADB

ILOADB : Number of buck cycles that occur within the cycle clock
bits : 0 - 7 (8 bit)


ILOAD_C

Buck Cycle Count VREGO_C Register
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ILOAD_C ILOAD_C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ILOADC

ILOADC : Number of buck cycles that occur within the cycle clock
bits : 0 - 7 (8 bit)


ILOAD_D

Buck Cycle Count VREGO_D Register
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ILOAD_D ILOAD_D read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ILOADD

ILOADD : Number of buck cycles that occur within the cycle clock
bits : 0 - 7 (8 bit)


BUCK_ALERT_THR_A

Buck Cycle Count Alert VERGO_A Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUCK_ALERT_THR_A BUCK_ALERT_THR_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUCKTHRA

BUCKTHRA : Threshold for ILOADA to generate the BUCK_ALERT
bits : 0 - 7 (8 bit)


BUCK_ALERT_THR_B

Buck Cycle Count Alert VERGO_B Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUCK_ALERT_THR_B BUCK_ALERT_THR_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUCKTHRB

BUCKTHRB : Threshold for ILOADB to generate the BUCK_ALERT
bits : 0 - 7 (8 bit)


BUCK_ALERT_THR_C

Buck Cycle Count Alert VERGO_C Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUCK_ALERT_THR_C BUCK_ALERT_THR_C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUCKTHRC

BUCKTHRC : Threshold for ILOADC to generate the BUCK_ALERT
bits : 0 - 7 (8 bit)


BUCK_ALERT_THR_D

Buck Cycle Count Alert VERGO_D Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUCK_ALERT_THR_D BUCK_ALERT_THR_D read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUCKTHRD

BUCKTHRD : Threshold for ILOADD to generate the BUCK_ALERT
bits : 0 - 7 (8 bit)


VREGO_A

Buck Voltage Regulator A Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREGO_A VREGO_A read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSETA RANGEA

VSETA : Regulator Output Voltage Setting
bits : 0 - 6 (7 bit)

RANGEA : Regulator Output Range Set
bits : 7 - 7 (1 bit)

Enumeration:

0 : low

Low output voltage range

1 : high

High output voltage range

End of enumeration elements list.


BUCK_OUT_READY

Buck Regulator Output Ready Register
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

BUCK_OUT_READY BUCK_OUT_READY read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUCKOUTRDYD BUCKOUTRDYC BUCKOUTRDYB BUCKOUTRDYA

BUCKOUTRDYD : When set, indicates that the output voltage has reached its regulated value
bits : 0 - 0 (1 bit)

BUCKOUTRDYC : When set, indicates that the output voltage has reached its regulated value
bits : 1 - 1 (1 bit)

BUCKOUTRDYB : When set, indicates that the output voltage has reached its regulated value
bits : 2 - 2 (1 bit)

BUCKOUTRDYA : When set, indicates that the output voltage has reached its regulated value
bits : 3 - 3 (1 bit)

Enumeration:

0 : notrdy

Output voltage not in range

1 : rdy

Output voltage in range

End of enumeration elements list.


ZERO_CROSS_CAL_A

Zero Cross Calibration VERGO_A Register
address_offset : 0x44 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ZERO_CROSS_CAL_A ZERO_CROSS_CAL_A read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZXCLA

ZXCLA : Zero Cross Calibrartion Value VREGO_A
bits : 0 - 3 (4 bit)


ZERO_CROSS_CAL_B

Zero Cross Calibration VERGO_B Register
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ZERO_CROSS_CAL_B ZERO_CROSS_CAL_B read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZXCLB

ZXCLB : Zero Cross Calibrartion Value VREGO_B
bits : 0 - 3 (4 bit)


ZERO_CROSS_CAL_C

Zero Cross Calibration VERGO_C Register
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ZERO_CROSS_CAL_C ZERO_CROSS_CAL_C read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZXCLC

ZXCLC : Zero Cross Calibrartion Value VREGO_C
bits : 0 - 3 (4 bit)


ZERO_CROSS_CAL_D

Zero Cross Calibration VERGO_D Register
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ZERO_CROSS_CAL_D ZERO_CROSS_CAL_D read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ZXCLD

ZXCLD : Zero Cross Calibrartion Value VREGO_D
bits : 0 - 3 (4 bit)


VREGO_B

Buck Voltage Regulator B Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREGO_B VREGO_B read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSETB RANGEB

VSETB : Regulator Output Voltage Setting
bits : 0 - 6 (7 bit)

RANGEB : Regulator Output Range Set
bits : 7 - 7 (1 bit)

Enumeration:

0 : low

Low output voltage range

1 : high

High output voltage range

End of enumeration elements list.


VREGO_C

Buck Voltage Regulator C Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREGO_C VREGO_C read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSETC RANGEC

VSETC : Regulator Output Voltage Setting
bits : 0 - 6 (7 bit)

RANGEC : Regulator Output Range Set
bits : 7 - 7 (1 bit)

Enumeration:

0 : low

Low output voltage range

1 : high

High output voltage range

End of enumeration elements list.



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