Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 31 (32 bit)
Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 15 (16 bit)
Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)
Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 15 (16 bit)
Register for reading and writing the FIFO.
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)
Register for reading and writing the FIFO.
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)
Register for reading and writing the FIFO.
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)
Register for controlling SPI peripheral.
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSACT1 : Slave Select Action delay 1.
bits : 0 - 7 (8 bit)
Enumeration:
0 : 256
256 system clocks between SS active and first serial clock edge.
End of enumeration elements list.
SSACT2 : Slave Select Action delay 2.
bits : 8 - 15 (8 bit)
Enumeration:
0 : 256
256 system clocks between last serial clock edge and SS inactive.
End of enumeration elements list.
SSINACT : Slave Select Inactive delay.
bits : 16 - 23 (8 bit)
Enumeration:
0 : 256
256 system clocks between transactions.
End of enumeration elements list.
Register for controlling SPI clock rate.
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOW : Low duty cycle control. In timer mode, reload[7:0].
bits : 0 - 7 (8 bit)
Enumeration:
0 : Dis
Duty cycle control of serial clock generation is disabled.
End of enumeration elements list.
HI : High duty cycle control. In timer mode, reload[15:8].
bits : 8 - 15 (8 bit)
Enumeration:
0 : Dis
Duty cycle control of serial clock generation is disabled.
End of enumeration elements list.
SCALE : System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.
bits : 16 - 19 (4 bit)
Register for controlling I2C mode.
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2S_EN : Low duty cycle control. In timer mode, reload[7:0].
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
I2C mode is disabled.
1 : en
I2C mode is enabled.
End of enumeration elements list.
I2S_MUTE : I2S Mute.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Normal Transmit.
1 : en
Transmit data is replaced with 0.
End of enumeration elements list.
I2S_PAUSE : I2S Pause.
bits : 2 - 2 (1 bit)
Enumeration:
0 : dis
Normal Transmit/Receive.
1 : en
Halt Transmit and Receive FIFO and DMA accesses, Transmit 0s.
End of enumeration elements list.
I2S_MONO : I2S Monotone.
bits : 3 - 3 (1 bit)
Enumeration:
0 : dis
Stereophonic audio format.
1 : en
Monophonic audio format. Each transmit data word is replicated on both left/right channels. Receive data is taken from left channel, right channel receive data is ignored.
End of enumeration elements list.
I2S_LJ : I2S Left Justify.
bits : 4 - 4 (1 bit)
Enumeration:
0 : dis
Normal I 2 S audio protocol, audio data lags left/right channel signal by one SCLK period.
1 : en
Audio data is synchronized with SSEL (left/right channel signal).
End of enumeration elements list.
Register for controlling DMA.
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FIFO_LEVEL : Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.
bits : 0 - 5 (6 bit)
TX_FIFO_EN : Transmit FIFO enabled for SPI transactions.
bits : 6 - 6 (1 bit)
Enumeration:
0 : dis
Transmit FIFO is not enabled.
1 : en
Transmit FIFO is enabled.
End of enumeration elements list.
TX_FIFO_CLEAR : Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
bits : 7 - 7 (1 bit)
Enumeration:
1 : CLEAR
Clear the Transmit FIFO, clears any pending TX FIFO status.
End of enumeration elements list.
TX_FIFO_CNT : Count of entries in TX FIFO.
bits : 8 - 12 (5 bit)
TX_DMA_EN : TX DMA Enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : DIS
TX DMA requests are disabled, andy pending DMA requests are cleared.
1 : en
TX DMA requests are enabled.
End of enumeration elements list.
RX_FIFO_LEVEL : Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.
bits : 16 - 21 (6 bit)
RX_FIFO_EN : Receive FIFO enabled for SPI transactions.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DIS
Receive FIFO is not enabled.
1 : en
Receive FIFO is enabled.
End of enumeration elements list.
RX_FIFO_CLEAR : Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.
bits : 23 - 23 (1 bit)
Enumeration:
1 : CLEAR
Clear the Receive FIFIO, clears any pending RX FIFO status.
End of enumeration elements list.
RX_FIFO_CNT : Count of entries in RX FIFO.
bits : 24 - 29 (6 bit)
RX_DMA_EN : RX DMA Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : dis
RX DMA requests are disabled, any pending DMA requests are cleared.
1 : en
RX DMA requests are enabled.
End of enumeration elements list.
Register for reading and writing the FIFO.
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 15 (16 bit)
Register for reading and writing the FIFO.
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 15 (16 bit)
Register for reading and writing the FIFO.
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)
Register for reading and clearing interrupt flags. All bits are write 1 to clear.
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THRESH : TX FIFO Threshold Crossed.
bits : 0 - 0 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
TX_EMPTY : TX FIFO Empty.
bits : 1 - 1 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
RX_THRESH : RX FIFO Threshold Crossed.
bits : 2 - 2 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
RX_FULL : RX FIFO FULL.
bits : 3 - 3 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SSA : Slave Select Asserted.
bits : 4 - 4 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SSD : Slave Select Deasserted.
bits : 5 - 5 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
FAULT : Multi-Master Mode Fault.
bits : 8 - 8 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
ABORT : Slave Abort Detected.
bits : 9 - 9 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
TIMEOUT : Timeout.
bits : 10 - 10 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
M_DONE : Master Done, set when SPI Master has completed any transactions.
bits : 11 - 11 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
TX_OVR : Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.
bits : 12 - 12 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
TX_UND : Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.
bits : 13 - 13 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
RX_OVR : Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.
bits : 14 - 14 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
RX_UND : Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.
bits : 15 - 15 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SR0A : Slave Ready 0 Asserted.
bits : 16 - 16 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SR1A : Slave Ready 1 Asserted.
bits : 17 - 17 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SR2A : Slave Ready 2 Asserted.
bits : 18 - 18 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SR3A : Slave Ready 3 Asserted.
bits : 19 - 19 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SR4A : Slave Ready 4 Asserted.
bits : 20 - 20 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SR5A : Slave Ready 5 Asserted.
bits : 21 - 21 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SR6A : Slave Ready 6 Asserted.
bits : 22 - 22 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
SR7A : Slave Ready 7 Asserted.
bits : 23 - 23 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
Register for enabling interrupts.
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THRESH : TX FIFO Threshold interrupt enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
TX_EMPTY : TX FIFO Empty interrupt enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
RX_THRESH : RX FIFO Threshold Crossed interrupt enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
RX_FULL : RX FIFO FULL interrupt enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SSA : Slave Select Asserted interrupt enable.
bits : 4 - 4 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SSD : Slave Select Deasserted interrupt enable.
bits : 5 - 5 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
FAULT : Multi-Master Mode Fault interrupt enable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
ABORT : Slave Abort Detected interrupt enable.
bits : 9 - 9 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
TIMEOUT : Timeout interrupt enable.
bits : 10 - 10 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
M_DONE : Master Done interrupt enable.
bits : 11 - 11 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
TX_OVR : Transmit FIFO Overrun interrupt enable.
bits : 12 - 12 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
TX_UND : Transmit FIFO Underrun interrupt enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
RX_OVR : Receive FIFO Overrun interrupt enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
RX_UND : Receive FIFO Underrun interrupt enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SR0A : Slave Ready 0 Asserted interrupt enable.
bits : 16 - 16 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SR1A : Slave Ready 1 Asserted interrupt enable.
bits : 17 - 17 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SR2A : Slave Ready 2 Asserted interrupt enable.
bits : 18 - 18 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SR3A : Slave Ready 3 Asserted interrupt enable.
bits : 19 - 19 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SR4A : Slave Ready 4 Asserted interrupt enable.
bits : 20 - 20 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SR5A : Slave Ready 5 Asserted interrupt enable.
bits : 21 - 21 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SR6A : Slave Ready 6 Asserted interrupt enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
SR7A : Slave Ready 7 Asserted interrupt enable.
bits : 23 - 23 (1 bit)
Enumeration:
0 : dis
Interrupt is disabled.
1 : en
Interrupt is enabled.
End of enumeration elements list.
Register for wake up flags. All bits in this register are write 1 to clear.
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THRESH : Wake on TX FIFO Threshold Crossed.
bits : 0 - 0 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
TX_EMPTY : Wake on TX FIFO Empty.
bits : 1 - 1 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
RX_THRESH : Wake on RX FIFO Threshold Crossed.
bits : 2 - 2 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
RX_FULL : Wake on RX FIFO Full.
bits : 3 - 3 (1 bit)
Enumeration:
1 : clear
Flag is set when value read is 1. Write 1 to clear this flag.
End of enumeration elements list.
Register for wake up enable.
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_THRESH : Wake on TX FIFO Threshold Crossed Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
Wakeup source disabled.
1 : en
Wakeup source enabled.
End of enumeration elements list.
TX_EMPTY : Wake on TX FIFO Empty Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
Wakeup source disabled.
1 : en
Wakeup source enabled.
End of enumeration elements list.
RX_THRESH : Wake on RX FIFO Threshold Crossed Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : dis
Wakeup source disabled.
1 : en
Wakeup source enabled.
End of enumeration elements list.
RX_FULL : Wake on RX FIFO Full Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : dis
Wakeup source disabled.
1 : en
Wakeup source enabled.
End of enumeration elements list.
Register for reading and writing the FIFO.
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)
Register for reading and writing the FIFO.
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)
SPI Status register.
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode.
bits : 0 - 0 (1 bit)
Enumeration:
0 : not
SPI not active.
1 : active
SPI active.
End of enumeration elements list.
Register to control external memory.
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RD_CMD : Read command.
bits : 0 - 7 (8 bit)
WR_CMD : Write command.
bits : 8 - 15 (8 bit)
DUMMY_CLK : Dummy clocks.
bits : 16 - 23 (8 bit)
XMEM_EN : XMEM enable.
bits : 31 - 31 (1 bit)
Register for controlling SPI peripheral.
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIEN : SPI Enable.
bits : 0 - 0 (1 bit)
Enumeration:
0 : dis
SPI is disabled.
1 : en
SPI is enabled.
End of enumeration elements list.
MMEN : Master Mode Enable.
bits : 1 - 1 (1 bit)
Enumeration:
0 : dis
SPI is Slave mode.
1 : en
SPI is Master mode.
End of enumeration elements list.
TIMER : Timer Enable.
bits : 2 - 2 (1 bit)
Enumeration:
0 : dis
Timer is disabled.
1 : en
Timer is enabled, only valid if SPIEN=0.
End of enumeration elements list.
FL_EN : Flow Control Mode Enable.
bits : 3 - 3 (1 bit)
Enumeration:
0 : dis
Flow Control mode is disabled.
1 : en
Flow Control Mode is enabled.
End of enumeration elements list.
SSIO : Slave Select 0, IO direction, to support Multi-Master mode, Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.
bits : 4 - 4 (1 bit)
Enumeration:
0 : output
Slave select 0 is output.
1 : input
Slave Select 0 is input, only valid if MMEN=1.
End of enumeration elements list.
TX_START : Start Transmit.
bits : 5 - 5 (1 bit)
Enumeration:
1 : start
Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction completes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.
End of enumeration elements list.
SS_CTRL : Slave Select Control.
bits : 8 - 8 (1 bit)
Enumeration:
0 : deassert
SPI de-asserts Slave Select at the end of a transaction.
1 : assert
SPI leaves Slave Select asserted at the end of a transaction.
End of enumeration elements list.
SS : Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.
bits : 16 - 23 (8 bit)
Enumeration:
0x1 : SS0
SS0 is selected.
0x2 : SS1
SS1 is selected.
0x4 : SS2
SS2 is selected.
0x8 : SS3
SS3 is selected.
0x10 : SS4
SS4 is selected.
0x20 : SS5
SS5 is selected.
0x40 : SS6
SS6 is selected.
0x80 : SS7
SS7 is selected.
End of enumeration elements list.
Register for reading and writing the FIFO.
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
alternate_register : DATA32
reset_Mask : 0x0
DATA : Read to pull from RX FIFO, write to put into TX FIFO.
bits : 0 - 7 (8 bit)
Register for controlling SPI peripheral.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_NUM_CHAR : Nubmer of Characters to transmit.
bits : 0 - 15 (16 bit)
RX_NUM_CHAR : Nubmer of Characters to receive.
bits : 16 - 31 (16 bit)
Register for controlling SPI peripheral.
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPHA : Clock Phase.
bits : 0 - 0 (1 bit)
CPOL : Clock Polarity.
bits : 1 - 1 (1 bit)
SCLK_FB_INV : Invert SCLK Feedback in Master Mode.
bits : 4 - 4 (1 bit)
Enumeration:
0 : NON_INV
SCLK is not inverted to Line Receiver.
1 : INV
SCLK is inverted to Line Receiver.
End of enumeration elements list.
NUMBITS : Number of Bits per character.
bits : 8 - 11 (4 bit)
Enumeration:
0 : 0
16 bits per character.
End of enumeration elements list.
DATA_WIDTH : SPI Data width.
bits : 12 - 13 (2 bit)
Enumeration:
0 : Mono
1 data pin.
1 : Dual
2 data pins.
2 : Quad
4 data pins.
End of enumeration elements list.
THREE_WIRE : Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire.
bits : 15 - 15 (1 bit)
Enumeration:
0 : dis
Use four wire mode (Mono only).
1 : en
Use three wire mode.
End of enumeration elements list.
SSPOL : Slave Select Polarity, each Slave Select can have unique polarity.
bits : 16 - 23 (8 bit)
Enumeration:
0x1 : SS0_high
SS0 active high.
0x2 : SS1_high
SS1 active high.
0x4 : SS2_high
SS2 active high.
0x8 : SS3_high
SS3 active high.
0x10 : SS4_high
SS4 active high.
0x20 : SS5_high
SS5 active high.
0x40 : SS6_high
SS6 active high.
0x80 : SS7_high
SS7 active high.
End of enumeration elements list.
SRPOL : Slave Ready Polarity, each Slave Ready can have unique polarity.
bits : 24 - 31 (8 bit)
Enumeration:
0x1 : SR0_high
SR0 active high.
0x2 : SR1_high
SR1 active high.
0x4 : SR2_high
SR2 active high.
0x8 : SR3_high
SR3 active high.
0x10 : SR4_high
SR4 active high.
0x20 : SR5_high
SR5 active high.
0x40 : SR6_high
SR6 active high.
0x80 : SR7_high
SR7 active high.
End of enumeration elements list.
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