\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
TRNG Control Register.
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODHT : Start On-Demand health test
bits : 0 - 0 (1 bit)
RND_IRQ_EN : To enable IRQ generation when a new 32-bit Random number is ready.
bits : 1 - 1 (1 bit)
Enumeration:
0 : disable
Disable
1 : enable
Enable
End of enumeration elements list.
HEALTH_EN : To enable IRQ generation when a health test fails
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : disable
disable
1 : enable
enable
End of enumeration elements list.
AESKG_MEU : AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.
bits : 3 - 3 (1 bit)
AESKG_MEMPROTE : AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.
bits : 4 - 4 (1 bit)
AESKG_MEMPROTA : AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.
bits : 5 - 5 (1 bit)
RSV16 : None
bits : 16 - 16 (1 bit)
RSV17 : None
bits : 17 - 17 (1 bit)
Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RND_RDY : 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1.
bits : 0 - 0 (1 bit)
Enumeration:
0 : Busy
TRNG Busy
1 : Ready
32 bit random data is ready
End of enumeration elements list.
ODHTS : On-Demand health test status
bits : 1 - 1 (1 bit)
Enumeration:
0 : Done
On demand health test done
1 : Busy
On demand health test on going
End of enumeration elements list.
HTS : Health test status. This bit shall be read when On-demand health test is completed (ODHTS=0) to check the result. This bit is also set when a continuous health test reports an error, IRQ is generated if HEALTH_EN=1. Write 1 to clear this bit.
bits : 2 - 2 (1 bit)
Enumeration:
0 : Pass
Pass
1 : Fail
Fail
End of enumeration elements list.
SRCFAIL : Entropy source has failed. IRQ is generated if HEALTH_EN=1. Write 1 to clear this bit.
bits : 3 - 3 (1 bit)
Enumeration:
0 : Works
Entopy source works correctly
1 : Fail
Entropy Source has failed
End of enumeration elements list.
AESKGD_MEU_S : Automatically AES transfer on going
bits : 4 - 4 (1 bit)
RSV16 : None
bits : 16 - 16 (1 bit)
Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATA : Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.
bits : 0 - 31 (32 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.