\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
NMI Source Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODOUT : BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BOD NMI source Disabled
#1 : 1
BOD NMI source Enabled
End of enumeration elements list.
IRC_INT : IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
IRC TRIM NMI source Disabled
#1 : 1
IRC TRIM NMI source Enabled
End of enumeration elements list.
PWRWU_INT : Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down mode wake-up NMI source Disabled
#1 : 1
Power-down mode wake-up NMI source Enabled
End of enumeration elements list.
SRAM_PERR : SRAM ParityCheck Error NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SRAM parity check error NMI source Disabled
#1 : 1
SRAM parity check error NMI source Enabled
End of enumeration elements list.
CLKFAIL : Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock fail detected and IRC Auto Trim interrupt NMI source Disabled
#1 : 1
Clock fail detected and IRC Auto Trim interrupt NMI source Enabled
End of enumeration elements list.
RTC_INT : RTC NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
RTC NMI source Disabled
#1 : 1
RTC NMI source Enabled
End of enumeration elements list.
EINT0 : External Interrupt From PA.6 or PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PA.6 or PB.5 pin NMI source Disabled
#1 : 1
External interrupt from PA.6 or PB.5 pin NMI source Enabled
End of enumeration elements list.
EINT1 : External Interrupt From PA.7, PB.4 or PD.15 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PA.7, PB.4 or PD.15 pin NMI source Disabled
#1 : 1
External interrupt from PA.7, PB.4 or PD.15 pin NMI source Enabled
End of enumeration elements list.
EINT2 : External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PB.3 or PC.6 pin NMI source Disabled
#1 : 1
External interrupt from PB.3 or PC.6 pin NMI source Enabled
End of enumeration elements list.
EINT3 : External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PB.2 or PC.7 pin NMI source Disabled
#1 : 1
External interrupt from PB.2 or PC.7 pin NMI source Enabled
End of enumeration elements list.
EINT4 : External Interrupt From PA.8, PB.6 or PF.15 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PA.8, PB.6 or PF.15 pin NMI source Disabled
#1 : 1
External interrupt from PA.8, PB.6 or PF.15 pin NMI source Enabled
End of enumeration elements list.
EINT5 : External Interrupt From PB.7, PD.12 or PF.14 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
External interrupt from PB.7, PD.12 or PF.14 pin NMI source Disabled
#1 : 1
External interrupt from PB.7, PD.12 or PF.14 pin NMI source Enabled
End of enumeration elements list.
UART0_INT : UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 NMI source Disabled
#1 : 1
UART0 NMI source Enabled
End of enumeration elements list.
UART1_INT : UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 NMI source Disabled
#1 : 1
UART1 NMI source Enabled
End of enumeration elements list.
NMI Source Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BODOUT : BOD Interrupt Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
BOD interrupt is deasserted
#1 : 1
BOD interrupt is asserted
End of enumeration elements list.
IRC_INT : IRC TRIM Interrupt Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
HIRC TRIM interrupt is deasserted
#1 : 1
HIRC TRIM interrupt is asserted
End of enumeration elements list.
PWRWU_INT : Power-down Mode Wake-up Interrupt Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
Power-down mode wake-up interrupt is deasserted
#1 : 1
Power-down mode wake-up interrupt is asserted
End of enumeration elements list.
SRAM_PERR : SRAM ParityCheck Error Interrupt Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
SRAM parity check error interrupt is deasserted
#1 : 1
SRAM parity check error interrupt is asserted
End of enumeration elements list.
CLKFAIL : Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
Clock fail detected or IRC Auto Trim interrupt is deasserted
#1 : 1
Clock fail detected or IRC Auto Trim interrupt is asserted
End of enumeration elements list.
RTC_INT : RTC Interrupt Flag (Read Only)
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
#0 : 0
RTC interrupt is deasserted
#1 : 1
RTC interrupt is asserted
End of enumeration elements list.
EINT0 : External Interrupt From PA.6 or PB.5 Pin Interrupt Flag (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PA.6 or PB.5 interrupt is deasserted
#1 : 1
External Interrupt from PA.6 or PB.5 interrupt is asserted
End of enumeration elements list.
EINT1 : External Interrupt From PA.7, PB.4 or PD.15 Pin Interrupt Flag (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PA.7, PB.4 or PD.15 interrupt is deasserted
#1 : 1
External Interrupt from PA.7, PB.4 or PD.15 interrupt is asserted
End of enumeration elements list.
EINT2 : External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only)
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PB.3 or PC.6 interrupt is deasserted
#1 : 1
External Interrupt from PB.3 or PC.6 interrupt is asserted
End of enumeration elements list.
EINT3 : External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only)
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PB.2 or PC.7 interrupt is deasserted
#1 : 1
External Interrupt from PB.2 or PC.7 interrupt is asserted
End of enumeration elements list.
EINT4 : External Interrupt From PA.8, PB.6 or PF.15 Pin Interrupt Flag (Read Only)
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PA.8, PB.6 or PF.15 interrupt is deasserted
#1 : 1
External Interrupt from PA.8, PB.6 or PF.15 interrupt is asserted
End of enumeration elements list.
EINT5 : External Interrupt From PB.7 or PF.14 Pin Interrupt Flag (Read Only)
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
External Interrupt from PB.7 or PF.14 interrupt is deasserted
#1 : 1
External Interrupt from PB.7 or PF.14 interrupt is asserted
End of enumeration elements list.
UART0_INT : UART0 Interrupt Flag (Read Only)
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
UART1 interrupt is deasserted
#1 : 1
UART1 interrupt is asserted
End of enumeration elements list.
UART1_INT : UART1 Interrupt Flag (Read Only)
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
UART1 interrupt is deasserted
#1 : 1
UART1 interrupt is asserted
End of enumeration elements list.
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