\n
address_offset : 0x0 Bytes (0x0)
size : 0x40 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x74 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
ADC Data Register 0
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSLT : A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC.
bits : 0 - 15 (16 bit)
access : read-only
OVERRUN : Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register, OVERRUN bit is set to 1. It is cleared by hardware after ADDR register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT bits is not overwritten
#1 : 1
Data in RSLT bits is overwritten
End of enumeration elements list.
VALID : Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT bits is not valid
#1 : 1
Data in RSLT bits is valid
End of enumeration elements list.
ADC Data Register 4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC PDMA Current Transfer Data Register
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURDAT : ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR15, and ADDR29 registers.
bits : 0 - 17 (18 bit)
access : read-only
ADC Data Register 5
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Calibration Mode Register
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALEN : Calibration Function Enable Bit\nNote: If chip is powered off, calibration function should be executed again.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Calibration function Disabled
End of enumeration elements list.
CALIE : Calibration Interrupt Enable Bit\nIf calibration function is enabled and the calibration finish, CALIF bit will be asserted, in the meanwhile, if CALIE bit is set to 1, a calibration interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Calibration function Interrupt Disabled
#1 : 1
Calibration function Interrupt Enabled
End of enumeration elements list.
ADC Calibration Status Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALIF : Calibration Finish Interrupt Flag\nIf calibration is finished, this flag will be set to 1. It is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
ADC Data Register 7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 8
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 9
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 10
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 11
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 12
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 13
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 14
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 15
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 29
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Data Register 2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : A/D Converter Enable Bit\nNote: Before starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter Disabled
#1 : 1
A/D converter Enabled
End of enumeration elements list.
ADIE : A/D Interrupt Enable Bit\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D interrupt function Disabled
#1 : 1
A/D interrupt function Enabled
End of enumeration elements list.
ADMD : A/D Converter Operation Mode Control\nNote 1: When changing the operation mode, software should clear ADST bit first.\nNote 2: In Burst mode, the A/D result data is always at ADC Data Register 0.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Single conversion
#01 : 1
Burst conversion
#10 : 2
Single-cycle Scan
#11 : 3
Continuous Scan
End of enumeration elements list.
TRGS : Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
A/D conversion is started by external STADC pin
#01 : 1
Timer0 ~ Timer3 overflow pulse trigger
#10 : 2
A/D conversion is started by BPWM trigger
#11 : 3
A/D conversion is started by PWM trigger
End of enumeration elements list.
TRGCOND : External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and at least 4 PCLKs for edge trigger.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Low level
#01 : 1
High level
#10 : 2
Falling edge
#11 : 3
Rising edge
End of enumeration elements list.
TRGEN : External Trigger Enable Bit\nEnable or disable triggering of A/D conversion by external STADC pin, PWM trigger, BPWM trigger and Timer trigger. If external trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.\nNote: The ADC external trigger function is only supported in Single-cycle Scan mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
External trigger Disabled
#1 : 1
External trigger Enabled
End of enumeration elements list.
PTEN : PDMA Transfer Enable Bit\nWhen A/D conversion is completed, the converted data is loaded into ADDR0~15, ADDR29. Software can enable this bit to generate a PDMA data transfer request.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA data transfer Disabled
#1 : 1
PDMA data transfer in ADDR0~15, ADDR29 Enabled
End of enumeration elements list.
DIFFEN : Differential Input Mode Control\nNote: In Differential Input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER register. The conversion result will be placed to the corresponding data register of the enabled channel.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single-end analog input mode
#1 : 1
Differential analog input mode
End of enumeration elements list.
ADST : A/D Conversion Start or Calibration Start\nADST bit can be set to 1 from four sources: software, external pin STADC, PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode, Single-cycle Scan mode and Calibration mode. In Continuous Scan mode and Burst mode, A/D conversion is continuously performed until software writes 0 to this bit or chip is reset.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stops and A/D converter enters idle state
#1 : 1
Conversion starts or Calibration Start
End of enumeration elements list.
RESET : ADC RESET (Write Protect)\nIf user writes this bit, the ADC analog macro will reset. Calibration data in macro will be deleted, but registers in ADC controller will keep.\nNote: This bit is cleared by hardware.
bits : 12 - 12 (1 bit)
access : read-write
DMOF : Differential Input Mode Output Format\nIf user enables differential input mode, the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format).
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D Conversion result will be filled in RSLT at ADDRx registers with unsigned format (straight binary format)
#1 : 1
A/D Conversion result will be filled in RSLT at ADDRx registers with 2's complement format
End of enumeration elements list.
ADC Channel Enable Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN : Analog Input Channel Enable Control\nSet ADCHER[15:0] bits to enable the corresponding analog input channel 15 ~ 0. If DIFFEN bit is set to 1, only the even number channel needs to be enabled.\nBesides, setting the ADCHER[29] bit will enable internal channel for band-gap voltage. Other bits are reserved.\nNote: If the internal channel for band-gap voltage (CHEN[29]) is active, the maximum sampling rate will be 300k SPS.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
Channel Disabled
1 : 1
Channel Enabled
End of enumeration elements list.
ADC Compare Register 0
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Enable Bit\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function Disabled
#1 : 1
Compare function Enabled
End of enumeration elements list.
CMPIE : Compare Interrupt Enable Bit\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPFx bit will be asserted, in the meanwhile, if CMPIE bit is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD bits, the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit A/D conversion result is greater than or equal to the 12-bit CMPD bits, the internal match counter will increase one
End of enumeration elements list.
CMPCH : Compare Channel Selection
bits : 3 - 7 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Channel 0 conversion result is selected to be compared
#00001 : 1
Channel 1 conversion result is selected to be compared
#00010 : 2
Channel 2 conversion result is selected to be compared
#00011 : 3
Channel 3 conversion result is selected to be compared
#00100 : 4
Channel 4 conversion result is selected to be compared
#00101 : 5
Channel 5 conversion result is selected to be compared
#00110 : 6
Channel 6 conversion result is selected to be compared
#00111 : 7
Channel 7 conversion result is selected to be compared
#01000 : 8
Channel 8 conversion result is selected to be compared
#01001 : 9
Channel 9 conversion result is selected to be compared
#01010 : 10
Channel 10 conversion result is selected to be compared
#01011 : 11
Channel 11 conversion result is selected to be compared
#01100 : 12
Channel 12 conversion result is selected to be compared
#01101 : 13
Channel 13 conversion result is selected to be compared
#01110 : 14
Channel 14 conversion result is selected to be compared
#01111 : 15
Channel 15 conversion result is selected to be compared
#11100 : 28
Floating detect channel conversion result is selected to be compared
#11101 : 29
Band-gap voltage conversion result is selected to be compared
End of enumeration elements list.
CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit, the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPFx bit will be set.
bits : 8 - 11 (4 bit)
access : read-write
CMPWEN : Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare Window Mode Disabled
#1 : 1
Compare Window Mode Enabled
End of enumeration elements list.
CMPD : Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format).
bits : 16 - 27 (12 bit)
access : read-write
ADC Compare Register 1
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC Status Register0
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.\nThe ADF bit is set to 1 at the following three conditions:\nWhen A/D conversion ends in Single mode.\nWhen A/D conversion ends on all specified channels in Single-cycle Scan mode and Continuous Scan mode.\nWhen more than or equal to 4 samples in FIFO in Burst mode.
bits : 0 - 0 (1 bit)
access : read-write
CMPF0 : Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet ADCMPR0 setting
#1 : 1
Conversion result in ADDR meets ADCMPR0 setting
End of enumeration elements list.
CMPF1 : Compare Flag 1
When the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register, this bit is set to 1 it is cleared by writing 1 to it
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet ADCMPR1 setting
#1 : 1
Conversion result in ADDR meets ADCMPR1 setting
End of enumeration elements list.
BUSY : BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
VALIDF : Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set, this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid, this flag will be set to 1.
bits : 8 - 8 (1 bit)
access : read-only
OVERRUNF : Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set, this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun, this flag will be set to 1.
bits : 16 - 16 (1 bit)
access : read-only
CHANNEL : Current Conversion Channel (Read Only)
bits : 27 - 31 (5 bit)
access : read-only
ADC Status Register1
address_offset : 0x94 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID : Data Valid Flag (Read Only)\nVALID[29, 15:0] are the mirror of the VALID bits in ADDR29[17], ADDR15[17]~ ADDR0[17]. The other bits are reserved.\nNote: When ADC is in burst mode and any conversion result is valid, VALID[29, 15:0] will be set to 1.
bits : 0 - 31 (32 bit)
access : read-only
ADC Status Register2
address_offset : 0x98 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVERRUN : Overrun Flag (Read Only)\nOVERRUN[29, 15:0] are the mirror of the OVERRUN bit in ADDR29[16], ADDR15[16] ~ ADDR0[16]. The other bits are reserved. \nNote: When ADC is in burst mode and the FIFO is overrun, OVERRUN[29, 15:0] will be set to 1.
bits : 0 - 31 (32 bit)
access : read-only
ADC Extend Sample Time Control Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTSMPT : ADC Sampling Time Extend \nWhen ADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend ADC sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock.
bits : 0 - 7 (8 bit)
access : read-write
ADC Channel Floating Detect Control Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRECHEN : Precharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel precharge Disabled
#1 : 1
Channel precharge Enabled
End of enumeration elements list.
DISCHEN : Discharge Enable\nNote: Analog input voltage is 1/2 VREF when PRECHEN and DISCHEN are all enable.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel discharge Disabled
#1 : 1
Channel discharge Enabled
End of enumeration elements list.
FDETCHEN : Floating Detect Channel Enable Bit
Note: if FDETCHEN is enabled, internal channel is always turn on.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Floating Detect Channel Disabled
#1 : 1
Floating Detect Channel Enabled
End of enumeration elements list.
ADC Data Register 3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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