\n
address_offset : 0x0 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x48 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 (BOD) Interrupt Source Identity
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BOD_INT : IRQ0 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ0 source is not from BOD interrupt (BOD_INT)
#1 : 1
IRQ0 source is from BOD interrupt (BOD_INT)
End of enumeration elements list.
IRQ4 (P0-P4) Interrupt Source Identity
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P0_INT : IRQ4 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ4 source is not from P0 interrupt (P0_INT)
#1 : 1
IRQ4 source is from P0 interrupt (P0_INT)
End of enumeration elements list.
P1_INT : IRQ4 Source Identity\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ4 source is not from P1 interrupt (P1_INT)
#1 : 1
IRQ4 source is from P1 interrupt (P1_INT)
End of enumeration elements list.
P2_INT : IRQ4 Source Identity\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ4 source is not from P2 interrupt (P2_INT)
#1 : 1
IRQ4 source is from P2 interrupt (P2_INT)
End of enumeration elements list.
P3_INT : IRQ4 Source Identity\n
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ4 source is not from P3 interrupt (P3_INT)
#1 : 1
IRQ4 source is from P3 interrupt (P3_INT)
End of enumeration elements list.
P4_INT : IRQ4 Source Identity\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ4 source is not from P4 interrupt (P4_INT)
#1 : 1
IRQ4 source is from P4 interrupt (P4_INT)
End of enumeration elements list.
IRQ5 (P5-PA) Interrupt Source Identity
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
P5_INT : IRQ5 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ5 source is not from P5 interrupt (P5_INT)
#1 : 1
IRQ5 source is from P5 interrupt (P5_INT)
End of enumeration elements list.
P6_INT : IRQ5 Source Identity\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ5 source is not from P6 interrupt (P6_INT)
#1 : 1
IRQ5 source is from P6 interrupt (P6_INT)
End of enumeration elements list.
P7_INT : IRQ5 Source Identity\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ5 source is not from P7 interrupt (P7_INT)
#1 : 1
IRQ5 source is from P7 interrupt (P7_INT)
End of enumeration elements list.
P8_INT : IRQ5 Source Identity\n
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ5 source is not from P8 interrupt (P8_INT)
#1 : 1
IRQ5 source is from P8 interrupt (P8_INT)
End of enumeration elements list.
P9_INT : IRQ5 Source Identity\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ5 source is not from P9 interrupt (P9_INT)
#1 : 1
IRQ5 source is from P9 interrupt (P9_INT)
End of enumeration elements list.
PA_INT : IRQ5 Source Identity\n
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ5 source is not from PA interrupt (PA_INT)
#1 : 1
IRQ5 source is from PA interrupt (PA_INT)
End of enumeration elements list.
IRQ6 (BPWM0) Interrupt Source Identity
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BPCH0_INT : IRQ6 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ6 source is not from BPWM0 channel 0 interrupt (BPCH0_INT)
#1 : 1
IRQ6 source is from BPWM0 channel 0 interrupt (BPCH0_INT)
End of enumeration elements list.
BPCH1_INT : IRQ6 Source Identity\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ6 source is not from BPWM0 channel 1 interrupt (BPCH1_INT)
#1 : 1
IRQ6 source is from BPWM0 channel 1 interrupt (BPCH1_INT)
End of enumeration elements list.
IRQ7 (EADC0) Interrupt Source Identity
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADC0_INT : IRQ7 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ7 source is not from EADC0 interrupt (EADC0_INT)
#1 : 1
IRQ7 source is from EADC0 interrupt (EADC0_INT)
End of enumeration elements list.
IRQ8 (TMR0) Interrupt Source Identity
address_offset : 0x20 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR0_INT : IRQ8 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ8 source is not from Timer0 interrupt (TMR0_INT)
#1 : 1
IRQ8 source is from Timer0 interrupt (TMR0_INT)
End of enumeration elements list.
IRQ9 (TMR1) Interrupt Source Identity
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR1_INT : IRQ9 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ9 source is not from Timer1 interrupt (TMR1_INT)
#1 : 1
IRQ9 source is from Timer1 interrupt (TMR1_INT)
End of enumeration elements list.
IRQ10 (TMR2) Interrupt Source Identity
address_offset : 0x28 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR2_INT : IRQ10 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ10 source is not from Timer2 interrupt (TMR2_INT)
#1 : 1
IRQ10 source is from Timer2 interrupt (TMR2_INT)
End of enumeration elements list.
IRQ11 (TMR3) Interrupt Source Identity
address_offset : 0x2C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TMR3_INT : IRQ11 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ11 source is not from Timer3 interrupt (TMR3_INT)
#1 : 1
IRQ11 source is from Timer3 interrupt (TMR3_INT)
End of enumeration elements list.
IRQ12 (UART0) Interrupt Source Identity
address_offset : 0x30 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UART0_INT : IRQ12 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ12 source is not from UART0 interrupt (UART0_INT)
#1 : 1
IRQ12 source is from UART0 interrupt (UART0_INT)
End of enumeration elements list.
IRQ13 (UART1) Interrupt Source Identity
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UART1_INT : IRQ13 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ13 source is not from UART1 interrupt (UART1_INT)
#1 : 1
IRQ13 source is from UART1 interrupt (UART1_INT)
End of enumeration elements list.
IRQ14 (SPI0) Interrupt Source Identity
address_offset : 0x38 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPI0_INT : IRQ14 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ14 source is not from SPI0 interrupt (SPI0_INT)
#1 : 1
IRQ14 source is from SPI0 interrupt (SPI0_INT)
End of enumeration elements list.
IRQ15 (SPI1) Interrupt Source Identity
address_offset : 0x3C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPI1_INT : IRQ15 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ15 source is not from SPI1 interrupt (SPI1_INT)
#1 : 1
IRQ15 source is from SPI1 interrupt (SPI1_INT)
End of enumeration elements list.
IRQ1 (WDT) Interrupt Source Identity
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDT_INT : IRQ1 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ1 source is not from watchdog interrupt (WDT _INT)
#1 : 1
IRQ1 source is from watchdog interrupt (WDT_INT)
End of enumeration elements list.
WWDT_INT : IRQ1 Source Identity\n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ1 source is not from window-watchdog interrupt (WWDT _INT)
#1 : 1
IRQ1 source is from window-watchdog interrupt (WWDT_INT)
End of enumeration elements list.
IRQ16 (SPI2) Interrupt Source Identity
address_offset : 0x40 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SPI2_INT : IRQ16 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ16 source is not from SPI2 interrupt (SPI2_INT)
#1 : 1
IRQ16 source is from SPI2 interrupt (SPI2_INT)
End of enumeration elements list.
IRQ18 (I2C0) Interrupt Source Identity
address_offset : 0x48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
I2C0_INT : IRQ18 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ18 source is not from I2C0 interrupt (I2C0_INT)
#1 : 1
IRQ18 source is from I2C0 interrupt (I2C0_INT)
End of enumeration elements list.
IRQ19 (CKD) Interrupt Source Identity
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CKD_INT : IRQ19 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ19 source is not from CKD interrupt (CKD_INT)
#1 : 1
IRQ19 source is from CKD interrupt (CKD_INT)
End of enumeration elements list.
IRQ21 (EPWM0) Interrupt Source Identity
address_offset : 0x54 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPWM0_INT : IRQ21 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ21 source is not from EPWM0 interrupt (EPWM0_INT)
#1 : 1
IRQ21 source is from EPWM0 interrupt (EPWM0_INT)
End of enumeration elements list.
IRQ22 (EPWM1) Interrupt Source Identity
address_offset : 0x58 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EPWM1_INT : IRQ22 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ22 source is not from EPWM1 interrupt (EPWM1_INT)
#1 : 1
IRQ22 source is from EPWM1 interrupt (EPWM1_INT)
End of enumeration elements list.
IRQ23 (ECAP0) Interrupt Source Identity
address_offset : 0x5C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECAP0_INT : IRQ23 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ23 source is not from ECAP0 interrupt (ECAP0_INT)
#1 : 1
IRQ23 source is from ECAP0 interrupt (ECAP0_INT)
End of enumeration elements list.
IRQ24 (ECAP1) Interrupt Source Identity
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ECAP1_INT : IRQ24 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ24 source is not from ECAP1 interrupt (ECAP1_INT)
#1 : 1
IRQ24 source is from ECAP1 interrupt (ECAP1_INT)
End of enumeration elements list.
IRQ25 (ACMP) Interrupt Source Identity
address_offset : 0x64 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACMP_INT : IRQ25 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ25 source is not from ACMP interrupt (ACMP_INT)
#1 : 1
IRQ25 source is from ACMP interrupt (ACMP_INT)
End of enumeration elements list.
IRQ28 (PWRWU) Interrupt Source Identity
address_offset : 0x70 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PWRWU_INT : IRQ28 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ28 source is not from PWRWU interrupt (PWRWU_INT)
#1 : 1
IRQ28 source is from PWREU interrupt (PWRWU_INT)
End of enumeration elements list.
IRQ29 (EADC1) Interrupt Source Identity
address_offset : 0x74 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADC1_INT : IRQ29 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ29 source is not from EADC1 interrupt (EADC1_INT)
#1 : 1
IRQ29 source is from EADC1 interrupt (EADC1_INT)
End of enumeration elements list.
IRQ30 (EADC2) Interrupt Source Identity
address_offset : 0x78 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADC2_INT : IRQ30 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ30 source is not from EADC2 interrupt (EADC2_INT)
#1 : 1
IRQ30 source is from EADC2 interrupt (EADC2_INT)
End of enumeration elements list.
IRQ31 (EADC3) Interrupt Source Identity
address_offset : 0x7C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EADC3_INT : IRQ31 Source Identity \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ31 source is not from EADC3 interrupt (EADC3_INT)
#1 : 1
IRQ31 source is from EADC3 interrupt (EADC3_INT)
End of enumeration elements list.
IRQ2 (EINT0) Interrupt Source Identity
address_offset : 0x8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EINT0 : IRQ2 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ2 source is not from external signal interrupt 0 from P3.2 (EINT0)
#1 : 1
IRQ2 source is from external signal interrupt 0 from P3.2 (EINT0)
End of enumeration elements list.
NMI Interrupt Source Select Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMI_SEL : NMI Interrupt Source Selection\nThe NMI interrupt to Cortex-M0 can be selected from one of IRQ0~IRQ31 by setting NMI_SEL with IRQ number. The default NMI interrupt is assigned as IRQ0 interrupt if NMI is enabled by setting NMI_SEL[8].
bits : 0 - 4 (5 bit)
access : read-write
NMI_EN : NMI Interrupt Enable Bit (Write Protect)\nNote: This bit is write protected bit. Refer to the REGWRPROT register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
IRQ0~31 assigned to NMI Disabled. (NMI still can be software triggered by setting its pending flag.)
#1 : 1
IRQ0~31 assigned to NMI Enabled
End of enumeration elements list.
MCU Interrupt Request Source Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MCU_IRQ : MCU IRQ Source Register\nThe MCU_IRQ collects all the interrupts from the peripherals and generates the synchronous interrupt to Cortex-M0.\nThe MCU_IRQ collects all interrupts from each peripheral and synchronizes them and then interrupts the Cortex-M0.\nWhen the MCU_IRQ[n] is 0, it means no interrupt is assert.\nWrite 1 to generate an interrupt to Cortex-M0 NVIC[n].\nWhen the MCU_IRQ[n] is 1, it means an interrupt is assert.\nWrite 1 to clear the interrupt and MCU_IRQ[n].
bits : 0 - 31 (32 bit)
access : read-write
MCU Interrupt Request Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FAST_IRQ : Fast IRQ Latency Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
MCU IRQ latency is fixed at 13 HCLK, MCU will enter IRQ handler after this fixed latency when interrupt happened
#1 : 1
MCU IRQ latency will not fixed, MCU will enter IRQ handler as soon as possible when interrupt happened
End of enumeration elements list.
IRQ3 (EINT1) Interrupt Source Identity
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EINT1 : IRQ3 Source Identity\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
IRQ3 source is not from external signal interrupt 1 from P3.3 (EINT1)
#1 : 1
IRQ3 source is from external signal interrupt 1 from P3.3 (EINT1)
End of enumeration elements list.
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