CPUID

SCR

SHPR2

SHPR3

ICSR

AIRCR

REVISION : Revision Number\nReads as 0x0.
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Part Number of the Processor\nReads as 0xC20 corresponding to Cortex-M0
bits : 4 - 15 (12 bit)
access : read-only

PART : Architecture of the Processor\nRead as 0xC corresponding to ARMv6-M architecture.
bits : 16 - 19 (4 bit)
access : read-only

IMPLEMENTER : Implementer Code Assigned by ARM \n
bits : 24 - 31 (8 bit)
access : read-only

SLEEPONEXIT : Sleep-on-exit Enable Bit\nThis bit controls sleep-on-exit when returning from Handler mode to Thread mode:\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEPDEEP : Deep Sleep Mode Enable Bit\nThis bit controls whether the processor uses sleep or deep sleep as its low power mode:\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEVONPEND : Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_11 : Priority of System Handler 11, SVCall 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority of System Handler 14, PendSV 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of System Handler 15, SysTick 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

VECTACTIVE : Vector Active Indicator (Read Only)\nThis field contains the active exception number:\n
bits : 0 - 5 (6 bit)
access : read-only

Enumeration:

End of enumeration elements list.

VECTPENDING : Vector Pending Indicator (Read Only)\nThis field indicates the exception number of the highest priority pending enabled exception:\n
bits : 12 - 17 (6 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISRPENDING : Interrupt Pending Flag (Read Only)\nIndicates if an external configurable (NVIC generated) interrupt is pending.\n
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PENDSTCLR : SysTick Exception Clear-pending Bit (Write Only)\n
bits : 25 - 25 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PENDSTSET : SysTick Exception Set-pending Bit\nWrite Operation:\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVCLR : PendSV Clear-pending Bit (Write Only)\n
bits : 27 - 27 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PENDSVSET : PendSV Set-pending Bit\nWrite Operation:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NMIPENDSET : NMI Set-pending Bit\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.\nWrite Operation:\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYSRESETREQ : System Reset Request (Write Only)\n
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

VECTKEY : Register Key (Write Only)\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.
bits : 16 - 31 (16 bit)
access : write-only