ISPCON

ISPTRG

DFBADR

FATCON

ISPADR

ISPSTA

ISPDAT

ISPCMD

ISPEN : ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect)\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : Config-bits Update Enable Bit (Write Protect)\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\nWrite 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP Start Trigger (Write Protect) Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. This bit is the protected bit, It means programming this bit needs to write 59h , 16h , 88h to address 0x5000_0100 to disable register protection. Refer to the register REGWRPROT at address GCR_BA+0x100 Note: To make sure ISP function has been finished before CPU goes ahead, ISB (Instruction Synchronization Barrier) instruction is used right after ISPGO (ISPTRG[0]) setting.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBADR : Data Flash Base Address\nThis register indicates data flash start address. It is read only.\nFor 128 KB flash memory device, the data flash size is defined by user configuration, register content is loaded from Config1 when chip is powered on but for 64 KB device, it is fixed at 0x0001_F000.
bits : 0 - 31 (32 bit)
access : read-only

FOM_SEL0 : Chip Frequency Optimization Mode Select (Write Protect)\n
bits : 4 - 4 (1 bit)
access : read-write

FOM_SEL1 : Chip Frequency Optimization Mode Select (Write Protect)\n
bits : 6 - 6 (1 bit)
access : read-write

ISPADR : ISP Address The NuMicro M0519 Series has a maximum 32Kx32 (128 KB) of embedded Flash, which supports word program only. ISPADR[1:0] must be kept 00b for ISP operation.
bits : 0 - 31 (32 bit)
access : read-write

ISPGO : ISP Start Trigger (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote: This bit is the same with ISPTRG bit0
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Chip Boot Selection of CONFIG (Read Only)\n
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (ISPCON[6]), it needs to be cleared by writing 1 to ISPCON[6] or FMC_ISPSTA[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) Page Erase command at LOCK mode with ICE connection\n(5) Erase or Program command at brown-out detected\n(6) Destination address is illegal, such as over an available range.\n(7) Invalid ISP commands\nWrite 1 to clear this bit.
bits : 6 - 6 (1 bit)
access : read-write

VECMAP : Vector Page Mapping Address (Read Only)\nThe current flash address space 0x0000_0000~0x0000_01FF is mapping to address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}\nNote: vector map function only workable when IAP mode enabled
bits : 9 - 20 (12 bit)
access : read-only

ISPDAT : ISP Data\nWrite data to this register before ISP program operation\nRead data from this register after ISP read operation
bits : 0 - 31 (32 bit)
access : read-write

CMD : ISP Command\nISP command table is shown below:\nThe other commands are invalid.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.