\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x240 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x280 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2E0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x148 byte (0x0)
mem_usage : registers
protection : not protected
GPIO Port 0 Pin I/O Mode Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMD0 : Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD1 : Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD2 : Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD3 : Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD4 : Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD5 : Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD6 : Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
PMD7 : Port 0-a I/O Pin[N] Mode Control\nDetermine each I/O mode of Px pins.\n
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [n] pin is in Input mode
#01 : 1
GPIO port [n] pin is in Push-pull Output mode
#10 : 2
GPIO port [n] pin is in Open-drain Output mode
#11 : 3
GPIO port [n] pin is in Quasi-bidirectional mode
End of enumeration elements list.
GPIO Port 0 Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN : Port 0-a Pin Values\nEach bit of the register reflects the actual status of the respective GPIO pin. If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.\n
bits : 0 - 7 (8 bit)
access : read-only
GPIO Port 4 Pin I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 4 Pin Digital Input Path Disable Control
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 4 Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 4 Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 4 Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 4 De-bounce Enable
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 4 Interrupt Mode Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 4 Interrupt Enable
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 4 Interrupt Source Flag
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 0 De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN : Port 0-a Input Signal De-bounce Enable Bits\nDBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt. The de-bounce clock source is controlled by DBCLKSRC (DBNCECON[4]), one de-bounce sample cycle period is controlled by DBCLKSEL (DBNCECON[3:0]).\n
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Bit[n] de-bounce function Disabled
1 : 1
Bit[n] de-bounce function Enabled
End of enumeration elements list.
GPIO Port 5 Pin I/O Mode Control
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 5 Pin Digital Input Path Disable Control
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 5 Data Output Value
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 5 Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 5 Pin Value
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 5 De-bounce Enable
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 5 Interrupt Mode Control
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 5 Interrupt Enable
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 5 Interrupt Source Flag
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 0 Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMD : Port 0-a Edge or Level Detection Interrupt Control\nIMD[n] decides the pin interrupt triggered by level or edge. If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce. If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.\n
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Edge triggered interrupt
1 : 1
Level triggered interrupt
End of enumeration elements list.
GPIO Port 6 Pin I/O Mode Control
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 6 Pin Digital Input Path Disable Control
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 6 Data Output Value
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 6 Data Output Write Mask
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 6 Pin Value
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 6 De-bounce Enable
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 6 Interrupt Mode Control
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 6 Interrupt Enable
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 0 Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF_EN : Port 0-a Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input Px_PIN[n]. Set bit to 1 also enable the pin wake-up function.
When setting the IF_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IR_EN : Port 0-a Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] used to enable the interrupt for each of the corresponding input Px_PIN[n]. Set bit to 1 also enable the pin wake-up function.
When setting the IR_EN[n] bit to 1:
If the interrupt is level trigger, the input PIN[n] state at level high will generate the interrupt.
If the interrupt is edge trigger, the input PIN[n] state change from low-to-high will generate the interrupt.
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
PIN[n] level-high or low-to-high interrupt Disabled
1 : 1
PIN[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
GPIO Port 7 Pin I/O Mode Control
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 7 Pin Digital Input Path Disable Control
address_offset : 0x1C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 7 Data Output Value
address_offset : 0x1C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 7 Data Output Write Mask
address_offset : 0x1CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 7 Pin Value
address_offset : 0x1D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 7 De-bounce Enable
address_offset : 0x1D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 7 Interrupt Mode Control
address_offset : 0x1D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 7 Interrupt Enable
address_offset : 0x1DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 7 Interrupt Source Flag
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 0 Interrupt Source Flag
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF_ISF : Port 0-a Interrupt Source Flag\nThese bits are edge/level trigger event indicators of each pin of Port x, if GPG0_INT or GPG1_INT enable bit is set, the corresponding interrupt service routine will be served. Note that P3.2 and P3.3 will only vector to INT0_INT and INT1_INT ISRs if its own interrupt is enabled.\nRead :\n
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
No interrupt at Px[n].\nNo action
1 : 1
Px[n] generates an interrupt.\nClear the corresponding pending interrupt
End of enumeration elements list.
GPIO Port 6 Interrupt Source Flag
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 8 Pin I/O Mode Control
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
alternate_register : P6_ISF
reset_Mask : 0x0
GPIO Port 8 Pin Digital Input Path Disable Control
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 8 Data Output Value
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 8 Data Output Write Mask
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 8 Pin Value
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 8 De-bounce Enable
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 8 Interrupt Mode Control
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 8 Interrupt Enable
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 8 Interrupt Source Flag
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 Pin I/O Mode Control
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 Pin Digital Input Path Disable Control
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 Data Output Value
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 Data Output Write Mask
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 Pin Value
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 De-bounce Enable
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 Interrupt Mode Control
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 Interrupt Enable
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 9 Interrupt Source Flag
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Pin I/O Mode Control
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Pin Digital Input Path Disable Control
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Data Output Value
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Data Output Write Mask
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Pin Value
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A De-bounce Enable
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Interrupt Mode Control
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Interrupt Enable
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Interrupt Source Flag
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
External Interrupt De-bounce Control
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce Sampling Cycle Selection\n
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Sample interrupt input once per 1 clocks
#0001 : 1
Sample interrupt input once per 2 clocks
#0010 : 2
Sample interrupt input once per 4 clocks
#0011 : 3
Sample interrupt input once per 8 clocks
#0100 : 4
Sample interrupt input once per 16 clocks
#0101 : 5
Sample interrupt input once per 32 clocks
#0110 : 6
Sample interrupt input once per 64 clocks
#0111 : 7
Sample interrupt input once per 128 clocks
#1000 : 8
Sample interrupt input once per 256 clocks
#1001 : 9
Sample interrupt input once per 2*256 clocks
#1010 : 10
Sample interrupt input once per 4*256 clocks
#1011 : 11
Sample interrupt input once per 8*256 clocks
#1100 : 12
Sample interrupt input once per 16*256 clocks
#1101 : 13
Sample interrupt input once per 32*256 clocks
#1110 : 14
Sample interrupt input once per 64*256 clocks
#1111 : 15
Sample interrupt input once per 128*256 clocks
End of enumeration elements list.
DBCLKSRC : De-bounce Counter Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter clock source is the HCLK
#1 : 1
De-bounce counter clock source is the internal 10 kHz low speed oscillator
End of enumeration elements list.
ICLK_ON : Interrupt Clock on Mode\nIt is recommended to turn off this bit to save system power if no special application concern.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge detection circuit is active only if I/O pin corresponding Px_IEN bit is set to 1
#1 : 1
All I/O pins edge detection circuit is always active after reset
End of enumeration elements list.
PWM Port Output Enable
address_offset : 0x2E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HZ_Even0 : Enhanced PWM Unit0 Even Ports Output Control\nNote: The initial value is loaded from CHZ_Even0 (Config0[8]) after any reset.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The driving mode of Enhanced PWM unit0 even ports are controlled by GPIO mode register (Px_PMD) or multi-function register (Px_MFP)
#1 : 1
The driving mode of Enhanced PWM unit0 even ports are forced in tri-state (Hi-Z) all the time
End of enumeration elements list.
HZ_Odd0 : Enhanced PWM Unit0 Odd Ports Output Control\nNote: The initial value is loaded from CHZ_Odd0 (Config0[9]) after any reset.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The driving mode of Enhanced PWM unit0 odd ports are controlled by GPIO mode register (Px_PMD) or multi-function register (Px_MFP)
#1 : 1
The driving mode of Enhanced PWM unit0 odd ports are forced in tri-state (Hi-Z) all the time
End of enumeration elements list.
HZ_Even1 : Enhanced PWM Unit1 Even Ports Output Control\nNote: The initial value is loaded from CHZ_Even1 (Config0[10]) after any reset.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The driving mode of Enhanced PWM unit1 even ports are controlled by GPIO mode register (Px_PMD) or multi-function register (Px_MFP)
#1 : 1
The driving mode of Enhanced PWM unit1 even ports are forced in tri-state (Hi-Z) all the time
End of enumeration elements list.
HZ_Odd1 : Enhanced PWM Unit1 Odd Ports Output Control\nNote: The initial value is loaded from CHZ_Odd1 (Config0[11]) after any reset.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The driving mode of Enhanced PWM unit1 odd ports are controlled by GPIO mode register (Px_PMD) or multi-function register (Px_MFP)
#1 : 1
The driving mode of Enhanced PWM unit1 odd ports are forced in tri-state (Hi-Z) all the time
End of enumeration elements list.
HZ_BPWM : Basic PWM0 Ports Output Control\nNote: The initial value is loaded from CHZ_BPWM (Config0[12]) after any reset.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The driving mode of Basic PWM ports are controlled by GPIO mode register
#1 : 1
The driving mode of Basic PWM ports are forced in tri-state (Hi-Z) all the time
End of enumeration elements list.
GPIO P0.n Pin Data Input/Output
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Pxn : GPIO Px.N Pin Data Input/Output\nWrite this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example: writing P0_0 will reflect the written value to bit P0_DOUT[0], read P0_0 will return the value of P0_PIN[0].\nNote: The write operation will not be affected by register Px_DMASK.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Corresponding GPIO pin set to low
#1 : 1
Corresponding GPIO pin set to high
End of enumeration elements list.
GPIO P0.n Pin Data Input/Output
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P0.n Pin Data Input/Output
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P1.n Pin Data Input/Output
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x358 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P2.n Pin Data Input/Output
address_offset : 0x35C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x360 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x364 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x368 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x36C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x370 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x374 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x378 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P3.n Pin Data Input/Output
address_offset : 0x37C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x380 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x384 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x388 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x38C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x390 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x394 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x398 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P4.n Pin Data Input/Output
address_offset : 0x39C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.n Pin Data Input/Output
address_offset : 0x3A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.n Pin Data Input/Output
address_offset : 0x3A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.n Pin Data Input/Output
address_offset : 0x3A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.n Pin Data Input/Output
address_offset : 0x3AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.n Pin Data Input/Output
address_offset : 0x3B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.n Pin Data Input/Output
address_offset : 0x3B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.n Pin Data Input/Output
address_offset : 0x3B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P5.n Pin Data Input/Output
address_offset : 0x3BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P6.n Pin Data Input/Output
address_offset : 0x3C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P6.n Pin Data Input/Output
address_offset : 0x3C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P6.n Pin Data Input/Output
address_offset : 0x3C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P6.n Pin Data Input/Output
address_offset : 0x3CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P6.n Pin Data Input/Output
address_offset : 0x3D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P6.n Pin Data Input/Output
address_offset : 0x3D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P6.n Pin Data Input/Output
address_offset : 0x3D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P6.n Pin Data Input/Output
address_offset : 0x3DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P7.n Pin Data Input/Output
address_offset : 0x3E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P7.n Pin Data Input/Output
address_offset : 0x3E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P7.n Pin Data Input/Output
address_offset : 0x3E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P7.n Pin Data Input/Output
address_offset : 0x3EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P7.n Pin Data Input/Output
address_offset : 0x3F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P7.n Pin Data Input/Output
address_offset : 0x3F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P7.n Pin Data Input/Output
address_offset : 0x3F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P7.n Pin Data Input/Output
address_offset : 0x3FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 0 Pin Digital Input Path Disable Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFD : Port 0-a Pin[N] Digital Input Path Disable Control\nEach of these bits is used to control if the digital input path of corresponding GPIO pin is disabled. If input is analog signal, users can disable GPIO digital input path to avoid input current leakage.\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
I/O digital input path Enabled
1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
GPIO Port 1 Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P8.n Pin Data Input/Output
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P8.n Pin Data Input/Output
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P8.n Pin Data Input/Output
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P8.n Pin Data Input/Output
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P8.n Pin Data Input/Output
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P8.n Pin Data Input/Output
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P8.n Pin Data Input/Output
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P8.n Pin Data Input/Output
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P9.n Pin Data Input/Output
address_offset : 0x420 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P9.n Pin Data Input/Output
address_offset : 0x424 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P9.n Pin Data Input/Output
address_offset : 0x428 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P9.n Pin Data Input/Output
address_offset : 0x42C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P9.n Pin Data Input/Output
address_offset : 0x430 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P9.n Pin Data Input/Output
address_offset : 0x434 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P9.n Pin Data Input/Output
address_offset : 0x438 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO P9.n Pin Data Input/Output
address_offset : 0x43C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 1 Pin Digital Input Path Disable Control
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x440 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO PA.n Pin Data Input/Output
address_offset : 0x444 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 1 Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 1 Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 1 Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 1 De-bounce Enable
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 1 Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 1 Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 1 Interrupt Source Flag
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 0 Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT : Port 0-a Pin[N] Output Value\nEach of these bits controls the status of a GPIO pin when the GPIO is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.\n
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[n] will drive Low if the GPIO pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode
1 : 1
GPIO port [0/1/2/3/4/5/6/7/8/9/A] Pin[n] will drive High if the GPIO pin is configured as Push-pull output or Quasi-bidirectional mode
End of enumeration elements list.
GPIO Port 2 Pin I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 2 Pin Digital Input Path Disable Control
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 2 Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 2 Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 2 Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 2 De-bounce Enable
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 2 Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 2 Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 2 Interrupt Source Flag
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 0 Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMASK : Port 0-a Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT bit[n]. When set the DMASK bit[n] is set to 1, the corresponding Px_DOUT[n] bit is protected. If the write signal is masked, write data to the protect bit is ignored.\n
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Corresponding Px_DOUT[n] bit can be updated
1 : 1
Corresponding Px_DOUT[n] bit protected
End of enumeration elements list.
GPIO Port 3 Pin I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 3 Pin Digital Input Path Disable Control
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 3 Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 3 Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 3 Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 3 De-bounce Enable
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 3 Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 3 Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port 3 Interrupt Source Flag
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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