TCSR2

TCAP2

TEXCON2

TEXISR2

TCSR3

TCMPR3

TISR3

TDR3

TCAP3

TEXCON3

TEXISR3

TCMPR2

TISR2

TDR2

PRESCALE : Prescale Counter\n
bits : 0 - 7 (8 bit)
access : read-write

TDR_EN : Data Load Enable Bit\nWhen this bit is set, timer counter value (TDR) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTB : Counter Mode Enable Bit \nThis bit is for external counting pin function enabled. \n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACT : Timer Active Status Bit (Read Only)\nThis bit indicates the up-timer status.\n
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CRST : Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value TDR and also force CEN (TCSR[30]) to 0 if CACT (TCSR[25]) is 1.\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE : Timer Counting Mode Select\n
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IE : Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CEN : Timer Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGACK_TMR : ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP : Timer Capture Data Register\n
bits : 0 - 23 (24 bit)
access : read-only

TX_PHASE : Timer External Count Phase \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEX_EDGE : Timer External Capture Pin Edge Detect\n
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXEN : Timer External Capture Pin Enable Bit\nThis bit enables the TMx pin. \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTCAPSEL : Capture Function Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXIEN : Timer External Capture Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXDB : Timer External Capture Pin De-bounce Enable Bit \nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCDB : Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEXIF : Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the TEXIF status. If the above condition occurred, the Timer will keep register TCAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCMP : Timer Compared Value\nTCMP is a 24-bit compared value register. When the internal 24-bit up counter value is equal to TCMP value, the TIF (TISR[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in TCMP field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into TCMP field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest TCMP value to be the timer compared value while user writes a new value into TCMP field.
bits : 0 - 23 (24 bit)
access : read-write

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter TDR value reaches to TCMP (TCMPR[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDR : Timer Data Register\nIf CTB (TCSR[24] ) is 0, user can read TDR value for getting current 24- bit counter value .\nIf CTB (TCSR[24] ) is 1, user can read TDR value for getting current 24- bit event input counter value.
bits : 0 - 23 (24 bit)
access : read-only