PPR

CMR0

PDR0

CNR1

CMR1

PDR1

CSR

PIER

PIIR

CCR

CRLR0

CFLR0

CRLR1

CFLR1

CAPENR

POE

PCR

CNR0

CP01 : Clock Prescaler\nClock input is divided by (CP01 + 1) before it is fed to the corresponding BPWM-timer\n
bits : 0 - 7 (8 bit)
access : read-write

DZI01 : Dead-zone Interval for Pair of Channel 0 and Channel 1\nThese 8-bit determine the Dead-zone length.\n
bits : 16 - 23 (8 bit)
access : read-write

CMR : BPWM Comparator Register\nCMR determines the BPWM duty.\nNote: Any write to CMR will take effect in next BPWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

PDR : BPWM Data Register\nUser can monitor PDR to know the current value in 16-bit counter.
bits : 0 - 15 (16 bit)
access : read-only

CSR0 : BPWM Timer 0 Clock Source Divider Selection\nSelect clock source divider for BPWM timer 0, please refer to CSR1
bits : 0 - 2 (3 bit)
access : read-write

CSR1 : BPWM Timer 1 Clock Source Divider Selection\nSelect clock source divider for BPWM timer 1.\n
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMPIE0 : BPWM Channel 0 Period Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMPIE1 : BPWM Channel 1 Period Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMDIE0 : BPWM Channel 0 Duty Interrupt Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMDIE1 : BPWM Channel 1 Duty Interrupt Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTTYPE : BPWM Interrupt Period Type Selection Bit\nNote: This bit is effective when BPWM in Center-aligned type only.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWMIF0 : BPWM Channel 0 Period Interrupt Flag\nThis bit is set by hardware when BPWM0_CH0 counter reaches the requirement of interrupt (depend on INTTYPE bit of PIER register). \nNote: This bit can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

BPWMIF1 : BPWM Channel 1 Period Interrupt Flag\nThis bit is set by hardware when BPWM0_CH1 counter reaches the requirement of interrupt (depend on INTTYPE bit of PIER register).\nNote: This bit can be cleared by writing '1' to it.
bits : 1 - 1 (1 bit)
access : read-write

BPWMDIF0 : BPWM Channel 0 Duty Interrupt Flag\nFlag is set by hardware when BPWM0_CH0 counter down count and reaches CMR0, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
bits : 8 - 8 (1 bit)
access : read-write

BPWMDIF1 : BPWM Channel 1 Duty Interrupt Flag\nFlag is set by hardware when BPWM0_CH1 counter down count and reaches CMR1, software can clear this bit by writing a one to it.\nNote: If CMR equal to CNR, this flag is not working in Edge-aligned type selection
bits : 9 - 9 (1 bit)
access : read-write

INV0 : Channel 0 Inverter Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE0 : Channel 0 Rising Latch Interrupt Enable Bit\nWhen Enabled, if capture detects BPWM0 channel 0 has rising transition, capture will issue an interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE0 : Channel 0 Falling Latch Interrupt Enable Bit\nWhen Enabled, if Capture detects BPWM0 channel 0 has falling transition, Capture will issue an Interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0EN : Channel 0 Capture Function Enable Bit\nWhen enabled, capture latched the BPWM0-counter value and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen disabled, capture does not update CRLR and CFLR, and disable BPWM0 channel 0 Interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Channel 0 Capture Interrupt Indication Flag\nNote: This bit can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-write

CRLRI0 : CRLR0 Latched Indicator Bit\nWhen BPWM0 input channel 0 has a rising transition, CRLR0 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-write

CFLRI0 : CFLR0 Latched Indicator Bit\nWhen BPWM0 input channel 0 has a falling transition, CFLR0 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it.
bits : 7 - 7 (1 bit)
access : read-write

INV1 : Channel 1 Inverter Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE1 : Channel 1 Rising Latch Interrupt Enable Bit\nWhen enabled, if capture detects BPWM0_CH1 has rising transition, capture will issue an interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE1 : Channel 1 Falling Latch Interrupt Enable Bit\nWhen enabled, if capture detects BPWM0_CH1 has falling transition, capture will issue an interrupt.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1EN : Channel 1 Capture Function Enable Bit\nWhen Enabled, Capture latched the BPWM0-counter and saved to CRLR (Rising latch) and CFLR (Falling latch).\nWhen disabled, capture does not update CRLR and CFLR, and disable BPWM0_CH1 interrupt.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF1 : Channel 1 Capture Interrupt Indication Flag\nNote: This bit can be cleared by writing '1' to it.
bits : 20 - 20 (1 bit)
access : read-write

CRLRI1 : CRLR1 Latched Indicator Bit\nWhen BPWM0 input channel 1 has a rising transition, CRLR1 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it.
bits : 22 - 22 (1 bit)
access : read-write

CFLRI1 : CFLR1 Latched Indicator Bit\nWhen BPWM0 input channel 1 has a falling transition, CFLR1 was latched with the value of BPWM0 down-counter and this bit is set by hardware.\nNote: This bit can be cleared by writing '1' to it.
bits : 23 - 23 (1 bit)
access : read-write

CRLR : Capture Rising Latch Register\nLatch the BPWM0 counter when Channel 0/1 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CFLR : Capture Falling Latch Register\nLatch the BPWM0 counter when Channel 0/1 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CINEN0 : Channel 0 Capture Input Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CINEN1 : Channel 1 Capture Input Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POE0 : Channel 0 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to BPWM0 function
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

POE1 : Channel 1 Output Enable Bit\nNote: The corresponding GPIO pin must also be switched to BPWM0 function
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0EN : BPWM-timer 0 Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0PINV : BPWM-timer 0 Output Polar Inverse Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0INV : BPWM-timer 0 Output Inverter Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0MOD : BPWM-timer 0 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit, it will cause CNR0 and CMR0 be cleared.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DZEN01 : Dead-zone 0 Generator Enable Bit\nNote: When Dead-zone generator is enabled, the pair of BPWM0_CH0 and BPWM0_CH1 becomes a complementary pair.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1EN : BPWM-timer 1 Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1PINV : BPWM-timer 1 Output Polar Inverse Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1INV : BPWM-timer 1 Output Inverter Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1MOD : BPWM-timer 1 Auto-reload/One-shot Mode\nNote: If there is a transition at this bit, it will cause CNR1 and CMR1 be cleared.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM01TYPE : BPWM0_CH0/1 Aligned Type Selection Bit \n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNR : BPWM Timer Loaded Value\nCNR determines the BPWM period.\nNote: Any write to CNR will take effect in next BPWM cycle.\nNote: When BPWM operating at Center-aligned type, CNR value should be set between 0x0000 to 0xFFFE. If CNR equal to 0xFFFF, the BPWM will work unpredictable.\nNote: When CNR value is set to 0, BPWM output is always high.
bits : 0 - 15 (16 bit)
access : read-write