Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x2C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
EPWM Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMMOD : PWM Mode Selection\n
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM mode is independent mode
#01 : 1
PWM mode is pair/complementary mode
#10 : 2
PWM mode is synchronized mode
#11 : 3
Reserved
End of enumeration elements list.
PWMDIV : PWM Clock Pre-divider Selection\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
PWM clock is EPWMx_CLK
#01 : 1
PWM clock is EPWMx_CLK/2
#10 : 2
PWM clock is EPWMx_CLK/4
#11 : 3
PWM clock is EPWMx_CLK/16
End of enumeration elements list.
PWMI_EN : PWM Interrupt Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flag PWMF (PWMSTS[2]) Disabled to trigger PWM interrupt
#1 : 1
Flag PWMF (PWMSTS[2]) Enabled to trigger PWM interrupt
End of enumeration elements list.
BRKI_EN : Brake0 and Brak1 Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flags BKF0 (PWMSTS[0]) and BKF1 (PWMSTS[1]) Disabled to trigger PWM interrupt
#1 : 1
Flags BKF0 (PWMSTS[0]) and BKF1 (PWMSTS[1]) Enabled to trigger PWM interrupt
End of enumeration elements list.
LOAD : Reload PWM Period Registers (PWMP) and PWM Duty Registers (PWM0~4) Control Bit\nNote: This bit is written by software, cleared by hardware, and always read as 0.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action if written with 0. The value of PWM period register (PWMP) and PWM duty registers (PWM0~PWM4) are not loaded to PWM counter and Comparator registers
#1 : 1
Hardware will update the value of PWM period register (PWMP) and PWM duty registers (PWM0~PWM4) to PWM Counter and Comparator register at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode
End of enumeration elements list.
PWMRUN : Start PWMRUN Control Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM stops running
#1 : 1
The PWM counter starts running
End of enumeration elements list.
INT_TYPE : PWM Interrupt Type Selection Bit\nNote: This bit is effective when PWM is in Center-aligned mode only.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMF will be set if PWM counter underflow
#1 : 1
PWMF will be set if PWM counter matches PWMP register
End of enumeration elements list.
PWMINV : Inverse PWM Comparator Output\nWhen PWMINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PWMINV is set to high.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not inverse PWM comparator output
#1 : 1
Inverse PWM comparator output
End of enumeration elements list.
CLRPWM : Clear PWM Counter Control Bit\nNote: It is automatically cleared by hardware.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Ignored
#1 : 1
Clear 16-bit PWM counter to 0000H
End of enumeration elements list.
PWMTYPE : PWM Aligned Type Selection Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-aligned type
#1 : 1
Center-aligned type
End of enumeration elements list.
GRP : Group Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 are independent
#1 : 1
Unify the signals timing of PWM_CH0, PWM_CH2 and PWM_CH4 in the same phase which is controlled by PWM_CH0
End of enumeration elements list.
INVBKP0 : Inverse Brake 0 Pin State\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin EPWMx_BRAKE0 is passed to the negative edge detector
#1 : 1
The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector
End of enumeration elements list.
INVBKP1 : Inverse Brake 1 Pin State\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin EPWMx_BRAKE1 is passed to the negative edge detector
#1 : 1
The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector
End of enumeration elements list.
BKEN0 : BRAKE0 Pin Trigger Brake Function 0 Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx brake function 0 Disabled
#1 : 1
PWMx brake function 0 Enabled
End of enumeration elements list.
BKEN1 : BRAKE1 Pin Trigger Brake Function 1 Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWMx brake function 1 Disabled
#1 : 1
PWMx brake function 1 Enabled
End of enumeration elements list.
BK1SEL : Brake Function 1 Source Selection\n
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
brake signal is from external pin EPWMx_BRAKE1 (x=0~1 for unit0~1)
#01 : 1
brake signal is from analog comparator 0 output CO0 (ACMPSR[8])
#10 : 2
brake signal is from analog comparator 1 output CO1 (ACMPSR[9])
#11 : 3
brake signal is from analog comparator 2 output CO2 (ACMPSR[10])
End of enumeration elements list.
BK0FILT : Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection\n
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
filter clock is HCLK
#01 : 1
filter clock is HCLK/2
#10 : 2
filter clock is HCLK/4
#11 : 3
filter clock is HCLK/16
End of enumeration elements list.
BK1FILT : Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection\n
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
filter clock is HCLK
#01 : 1
filter clock is HCLK/2
#10 : 2
filter clock is HCLK/4
#11 : 3
filter clock is HCLK/16
End of enumeration elements list.
CPO0BK_EN : ACMP0 Digital Output As Brake0 Source Enable Bit\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
CO0 (ACMPSR[8]) as one brake source in Brake 0 Disabled
#1 : 1
CO0 (ACMPSR[8]) as one brake source in Brake 0 Enabled
End of enumeration elements list.
CPO1BK_EN : ACMP1 Digital Output As Brake 0 Source Enable Bit\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
CO1 (ACMPSR[9]) as one brake source in Brake 0 Disabled
#1 : 1
CO1 (ACMPSR[9]) as one brake source in Brake 0 Enabled
End of enumeration elements list.
CPO2BK_EN : ACMP2 Digital Output As Brake 0 Source Enable Bit\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
CO2 (ACMPSR[10]) as one brake source in Brake 0 Disabled
#1 : 1
CO2 (ACMPSR[10]) as one brake source in Brake 0 Enabled
End of enumeration elements list.
LVDBK_EN : Low-level Detection Trigger PWM Brake Function 1 Enable Bit\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function 1 triggered by Low-level detection Disabled
#1 : 1
Brake Function 1 triggered by Low-level detection Enabled
End of enumeration elements list.
BK0NF_DIS : PWM Brake 0 Noise Filter Disable Bit\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 0 Enabled
#1 : 1
Noise filter of PWM Brake 0 Disabled
End of enumeration elements list.
BK1NF_DIS : PWM Brake 1 Noise Filter Disable Bit\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of PWM Brake 1 Enabled
#1 : 1
Noise filter of PWM Brake 1 Disabled
End of enumeration elements list.
CLDMD : Center Reload Mode Enable Bit\nThis bit only works when EPWM operating in Center-aligned mode.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM reload duty register at the period point of PWM counter
#1 : 1
EPWM reload duty register at the center point of PWM counter
End of enumeration elements list.
EPWM PWM2 Duty Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM PWM4 Duty Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Mask Mode Enable Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMSKE : PWM Mask Enable Bits\nThe PWM generator signal will be masked when this bit is enabled. The corresponding PWM channel n will be output with PMSKD[n] data. \n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM generator signal is output to next stage
1 : 1
PWM generator signal is masked and PMSKD[n] is output to next stage, n = 0~5
End of enumeration elements list.
EPWM Mask Mode Data Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMSKD : PWM Mask Data Bit\n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
Output logic low to PWM_CHn
1 : 1
Output logic high to PWM_CHn
End of enumeration elements list.
EPWM Dead-time Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT : Dead-time Counter\nThe dead-time can be calculated according to the following formula: \n
bits : 0 - 10 (11 bit)
access : read-write
DTEN0 : Enable Dead-time Insertion for PWMx Pair (PWM_CH0, PWM_CH1)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM_CH0, PWM_CH1)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM_CH0, PWM_CH1)
End of enumeration elements list.
DTEN2 : Enable Dead-time Insertion for PWMx Pair (PWM_CH2, PWM_CH3)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM_CH2, PWM_CH3)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM_CH2, PWM_CH3)
End of enumeration elements list.
DTEN4 : Enable Dead-time Insertion for PWMx Pair (PWM_CH4, PWM_CH5)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair (PWM_CH4, PWM_CH5)
#1 : 1
Dead-time insertion Enabled on the pin pair (PWM_CH4, PWM_CH5)
End of enumeration elements list.
EPWM Brake Output Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMB : PWM Brake Output\n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM_CHn output before polarity control is low when Brake is asserted
1 : 1
PWM_CHn output before polarity control is high when Brake is asserted
End of enumeration elements list.
EPWM Negative Polarity Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PNP : PWM Negative Polarity Control\n
bits : 0 - 5 (6 bit)
access : read-write
Enumeration:
0 : 0
PWM_CHn output is active high
1 : 1
PWM_CHn output is active low
End of enumeration elements list.
EPWMF Compared Counter Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMFCNT : PWMF Compared Counter\nThe register sets the count number which defines how many times of PWM period occurs to set bit PWMF (PWMSTS[2]) to request the PWM period interrupt. \nPWMF (PWMSTS[2]) will be set in every (PWMFCNT[3:0] + 1) times of PWM period or center point defined by INT_TYPE at PWMCON[8] occurs
bits : 0 - 3 (4 bit)
access : read-write
EPWM Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BKF0 : PWM Brake0 Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake 0 is able to poll falling signal at EPWMx_BRAKE0, x=0, 1 and has not recognized any one
#1 : 1
When PWM Brake 0 detects a falling signal at EPWMx_BRAKE0, x=0, 1, this flag will be set to high
End of enumeration elements list.
BKF1 : PWM Brake1 Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM Brake 1 is able to poll falling signal at EPWMx_BRAKE1, x=0, 1 and has not recognized any one
#1 : 1
When PWM Brake 1 detects a falling signal at pin EPWMx_BRAKE1, x=0, 1, this flag will be set to high
End of enumeration elements list.
PWMF : PWM Period Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PWM Counter has not up counted to the value of PWMP or down counted with underflow
#1 : 1
Hardware will set this flag to high at the time of PWM Counter matches PWMP in Edge- and Center-aligned modes or at the time of PWM Counter down counts with underflow in Center-aligned mode
End of enumeration elements list.
PWM0EF : PWM Channel 0 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH0 not toggled
#1 : 1
Hardware will set this flag to high at the time of PWM_CH0 rising or falling. If EINT0_TYPE (PWMEIC[8]) = 0, this bit is set when PWM_CH0 falling is detected. If EINT0_TYPE (PWMEIC[8]) = 1, this bit is set when PWM_CH0 rising is detected
End of enumeration elements list.
PWM2EF : PWM Channel 2 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH2 not toggled
#1 : 1
Hardware will set this flag to high at the time of PWM_CH2 rising or falling. If EINT2_TYPE (PWMEIC[9]) = 0, this bit is set when PWM_CH2 falling is detected. If EINT2_TYPE (PWMEIC[9]) = 1, this bit is set when PWM_CH2 rising is detected
End of enumeration elements list.
PWM4EF : PWM Channel 4 Edge Flag\nNote: This bit must be cleared by writing 1 to itself through software.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM_CH4 not toggled
#1 : 1
Hardware will set this flag to high at the time of PWM_CH4 rising or falling. If EINT4_TYPE (PWMEIC[10]) = 0, this bit is set when PWM_CH4 falling is detected. If EINT4_TYPE (PWMEIC[10]) = 1, this bit is set when PWM_CH4 rising is detected
End of enumeration elements list.
BKLK0 : PWM Brake 0 Locked \nNote: This bit must be cleared by writing 1 to itself through software.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 0 state is released
#1 : 1
When PWM Brake detects a falling signal at EPWMx_BRAKE0, x=0, 1. This flag will be set to high to indicate the Brake 0 state is locked
End of enumeration elements list.
BK0STS : Brake 0 Status (Read Only)\n
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM had been out of Brake 0 state
#1 : 1
PWM is in Brake 0 state
End of enumeration elements list.
BK1STS : Brake 1 Status (Read Only)\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
PWM had been out of Brake 1 state
#1 : 1
PWM is in Brake 1 state
End of enumeration elements list.
EPWM Edge Interrupt Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM0EI_EN : Enable PWM Channel 0 Edge Interrupt\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flag PWM0EF Disabled to trigger PWM interrupt
#1 : 1
Flag PWM0EF Enabled to trigger PWM interrupt
End of enumeration elements list.
PWM2EI_EN : Enable PWM Channel 2 Edge Interrupt\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flag PWM2EF Disabled to trigger PWM interrupt
#1 : 1
Flag PWM2EF Enabled to trigger PWM interrupt
End of enumeration elements list.
PWM4EI_EN : Enable PWM Channel 4 Edge Interrupt\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flag PWM4EF Disabled to trigger PWM interrupt
#1 : 1
Flag PWM4EF Enabled to trigger PWM interrupt
End of enumeration elements list.
EINT0_TYPE : PWM Channel 0 Edge Interrupt Type\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0EF will be set if falling edge is detected at PWM_CH0
#1 : 1
PWM0EF will be set if rising edge is detected at PWM_CH0
End of enumeration elements list.
EINT2_TYPE : PWM Channel 2 Edge Interrupt Type\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM2EF will be set if falling edge is detected at PWM_CH2
#1 : 1
PWM2EF will be set if rising edge is detected at PWM_CH2
End of enumeration elements list.
EINT4_TYPE : PWM Channel 4 Edge Interrupt Type\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM4EF will be set if falling edge is detected at PWM_CH4
#1 : 1
PWM4EF will be set if rising edge is detected at PWM_CH4
End of enumeration elements list.
EPWM Period Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWMP : PWM Period Register\nEdge-aligned:\n
bits : 0 - 15 (16 bit)
access : read-write
EPWM PWM0 Duty Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM_Duty : PWM Duty Register\nEdge-aligned:\n
bits : 0 - 15 (16 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.