\n

WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WTCR

WTCRALT


WTCR

WDT Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCR WTCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTR WTRE WTRF WTIF WTWKE WTWKF WTIE WTE WTIS DBGACK_WDT

WTR : Reset WDT Up Counter (Write Protect)\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: This bit will be automatically cleared by hardware.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset the internal 18-bit WDT up counter value

End of enumeration elements list.

WTRE : WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT time-out reset function Disabled

#1 : 1

WDT time-out reset function Enabled

End of enumeration elements list.

WTRF : WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT time-out reset did not occur

#1 : 1

WDT time-out reset occurred

End of enumeration elements list.

WTIF : WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT time-out interrupt did not occur

#1 : 1

WDT time-out interrupt occurred

End of enumeration elements list.

WTWKE : WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1, while WDT time-out interrupt flag IF (WTCR[3]) is generated to 1 and interrupt enable bit WTIE (WTCR[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz internal low speed RC oscillator (LIRC).
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Wake-up trigger event Disabled if WDT time-out interrupt signal generated

#1 : 1

Wake-up trigger event Enabled if WDT time-out interrupt signal generated

End of enumeration elements list.

WTWKF : WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT does not cause chip wake-up

#1 : 1

Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated

End of enumeration elements list.

WTIE : WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU. \nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT time-out interrupt Disabled

#1 : 1

WDT time-out interrupt Enabled

End of enumeration elements list.

WTE : WDT Enable Bit (Write Protect)\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: If CWDTEN (Config0[31]) bits is configure to 0, this bit is forced as 1 and user cannot change this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

WDT Disabled (This action will reset the internal up counter value)

#1 : 1

WDT Enabled

End of enumeration elements list.

WTIS : WDT Time-out Interval Selection (Write Protect)\nThese three bits select the time-out interval period for the WDT.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

24 * WDT_CLK

#001 : 1

26 * WDT_CLK

#010 : 2

28 * WDT_CLK

#011 : 3

210 * WDT_CLK

#100 : 4

212 * WDT_CLK

#101 : 5

214 * WDT_CLK

#110 : 6

216 * WDT_CLK

#111 : 7

218 * WDT_CLK

End of enumeration elements list.

DBGACK_WDT : ICE Debug Mode Acknowledge Disable (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the REGWRPROT register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement affects WDT counting

#1 : 1

ICE debug mode acknowledgement Disabled

End of enumeration elements list.


WTCRALT

WDT Alternative Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WTCRALT WTCRALT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTRDSEL

WTRDSEL : WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting WTR (WTCR[0]) to prevent WDT time-out reset happened. User can select a suitable setting of WTRDSEL for different WDT Reset Delay Period.\nNote1: This bit is write protected. Refer to the REGWRPROT register.\nNote2: This register will be reset to 0 if WDT time-out reset happened.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

WDT Reset Delay Period is 1026 * WDT_CLK

#01 : 1

WDT Reset Delay Period is 130 * WDT_CLK

#10 : 2

WDT Reset Delay Period is 18 * WDT_CLK

#11 : 3

WDT Reset Delay Period is 3 * WDT_CLK

End of enumeration elements list.



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