UA_RBR

UA_THR

UA_MCR

UA_MSR

UA_FSR

UA_ISR

UA_TOR

UA_BAUD

UA_IRCR

UA_ALT_CSR

UA_FUN_SEL

UA_LIN_CTL

UA_LIN_SR

UA_IER

UA_FCR

UA_LCR

RBR : Receive Buffer Register (Read Only)\nBy reading this register, the UART will return an 8-bit data received from UART_RXD pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only

THR : Transmit Holding Register\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD pin. (LSB first)
bits : 0 - 7 (8 bit)
access : write-only

RTS : nRTS (Request-to-send) Signal\nThis bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with LEV_RTS bit configuration.\nNote1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.\nNote2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LEV_RTS : nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 678 and Figure 679 for UART function mode.\nNote2: Refer to Figure 682 and Figure 683 for RS-485 function mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_ST : nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.\n
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DCTSF : Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEM_IEN (UA_IER[3]) is set to 1.\nWrite 1 to clear this bit to 0
bits : 0 - 0 (1 bit)
access : read-write

CTS_ST : nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LEV_CTS : nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_OVER_IF : RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UA_RBR) size, this bit will be set.\nNote: This bit can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_ADD_DETF : RS-485 Address Byte Detection Flag \nNote1: This field is used for RS-485 function mode and RS485_ADD_EN (UA_ALT_CSR[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PEF : Parity Error Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note: This bit can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FEF : Frame Error Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0). Note: This bit can be cleared by writing '1' to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIF : Break Error Interrupt Flag This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_POINTER : RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER increases one. When one byte of RX FIFO is read by CPU, RX_POINTER decreases one.\nThe Maximum value shown in RX_POINTER is 15. When the using level of RX FIFO Buffer equal to 16, the RX_FULL bit is set to 1 and RX_POINTER will show 0. As one byte of RX FIFO is read by CPU, the RX_FULL bit is cleared to 0 and RX_POINTER will show 15.
bits : 8 - 13 (6 bit)
access : read-only

RX_EMPTY : Receiver FIFO Empty (Read Only)\nThis bit indicates RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_FULL : Receiver FIFO Full (Read Only)\nThis bit indicates RX FIFO is full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_POINTER : TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UA_THR, TX_POINTER increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TX_POINTER decreases one.\nThe Maximum value shown in TX_POINTER is 15. When the using level of TX FIFO Buffer equal to 16, the TX_FULL bit is set to 1 and TX_POINTER will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TX_FULL bit is cleared to 0 and TX_POINTER will show 15.
bits : 16 - 21 (6 bit)
access : read-only

TX_EMPTY : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO is empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into UA_THR (TX FIFO not empty).
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_FULL : Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO is full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer equal to 16, otherwise it is cleared by hardware.
bits : 23 - 23 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_OVER_IF : TX Overflow Error Interrupt Flag\nIf TX FIFO (UA_THR) is full, an additional write to UA_THR will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TE_FLAG : Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDA_IF : Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL (UA_FCR[7:4]) then the RDA_IF (UA_ISR[0]) will be set. If RDA_IEN (UA_IER [0]) is enabled, the RDA interrupt will be generated. \nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL (UA_FCR[7:4])).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRE_IF : Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THRE_IEN (UA_IER [1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLS_IF : Receive Line Interrupt Flag (Read Only) This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]), is set). If RLS_IEN (UA_IER [2]) is enabled, the RLS interrupt will be generated. Note2: This bit is read only and reset to 0 when all bits of BIF (UA_FSR[6]), FEF (UA_FSR[5]) and PEF (UA_FSR[4]) are cleared. Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UA_FSR[6]) , FEF(UA_FSR[5]) and PEF(UA_FSR[4]) and RS485_ADD_DETF (UA_FSR[3]) are cleared.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEM_IF : MODEM Interrupt Flag (Read Only)\nNote: This bit is reset to 0 when bit DCTSF (UA_MSR[0]) is cleared by a write 1 on DCTSF (UA_MSR[0]).
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUT_IF : Time Out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time out counter equal to TOIC (UA_TOR[7:0]). If TOUT_IEN (UA_IER [4]) is enabled, the time-out interrupt will be generated. \nNote: User can read UA_RBR (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUF_ERR_IF : Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TX_OVER_IF (UA_FSR[24]) or RX_OVER_IF (UA_FSR[0]) is set. When BUF_ERR_IF (UA_ISR[5]) is set, the transfer is not correct. If BUF_ERR_IEN (UA_IER [5]) is enabled, the buffer error interrupt will be generated.\nNote: This bit is cleared if both of RX_OVER_IF (UA_FSR[0]) and TX_OVER_IF (UA_FSR[24]) are cleared to 0 by writing 1 to RX_OVER_IF (UA_FSR[0]) and TX_OVER_IF (UA_FSR[24]).
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIN_IF : LIN Bus Flag (Read Only)\nNote: This bit is read only. This bit is cleared when LINS_HDET_F (UA_LIN_SR[0]), LIN_BKDET_F (UA_LIN_SR[8]), BIT_ERR_F (UA_LIN_SR[9]), LINS_IDPENR_F (UA_LIN_SR[2]) and LINS_HERR_F (UA_LIN_SR[1]) all are cleared.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RDA_INT : Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDA_IEN (UA_IER[0]) and RDA_IF (UA_ISR[0]) are both set to 1.\n
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRE_INT : Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THRE_IEN (UA_IER[1]) and THRE_IF (UA_ISR[1]) are both set to 1.\n
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLS_INT : Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLS_IEN (UA_IER[2] and RLS_IF (UA_ISR[2]) are both set to 1.\n
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEM_INT : MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEM_IEN (UA_IER[3]) and MODEM_IF (UA_ISR[3]) are both set to 1.\n
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUT_INT : Time Out Interrupt Indicator (Read Only)\nThis bit is set if TOUT_IEN (UA_IER[4]) and TOUT_IF (UA_ISR[4]) are both set to 1.\n
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUF_ERR_INT : Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUF_ERR_IEN (UA_IER[5]) and BUF_ERR_IF (UA_ISR[5]) are both set to 1.\n
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIN_INT : LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LIN_IEN (UA_IER[8]) and LIN _IF (UA_ISR[7]) are both set to 1.\n
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time Out Interrupt Comparator\n
bits : 0 - 7 (8 bit)
access : read-write

DLY : TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time.
bits : 8 - 15 (8 bit)
access : read-write

BRD : Baud Rate Divider\nThe field indicates the baud rate divider. This filed is used in baud rate calculation.\nNote: The detail description is shown in UART Controller Baud Rate Generator section.
bits : 0 - 15 (16 bit)
access : read-write

DIVIDER_X : Divider X\nNote 1: This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.\nNote 2: The detail description is shown in UART Controller Baud Rate Generator section.
bits : 24 - 27 (4 bit)
access : read-write

DIV_X_ONE : Divider X Equal to 1\nNote: The detail description is shown in UART Controller Baud Rate Generator section.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV_X_EN : Divider X Enable Bit\nNote1: The detail description is shown in UART Controller Baud Rate Generator section.\nNote2: In IrDA mode, this bit must disable.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_SELECT : IrDA Receiver/Transmitter Selection Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_TX : IrDA Inverse Transmitting Output Signal\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_RX : IrDA Inverse Receive Input Signal\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_BKFL : UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is UA_LIN_BKFL + 1.\n
bits : 0 - 3 (4 bit)
access : read-write

LIN_RX_EN : LIN RX Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_EN : LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished, this bit will be cleared automatically.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_NMM : RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_AAD : RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_AUD : RS-485 Auto Direction Mode (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485_ADD_EN : RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This field is used for RS-485 any operation mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR_MATCH : Address Match Value Register \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode.
bits : 24 - 31 (8 bit)
access : read-write

FUN_SEL : Function Select Enable Bit\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINS_EN : LIN Slave Mode Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINS_HDET_EN : LIN Slave Header Detection Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINS_ARS_EN : LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode, the baud rate setting must be mode2 (DIV_X_EN (UA_BAUD [29]) and DIV_X_ONE (UA_BAUD [28]) must be 1).\nNote3: The control and interactions of this field are explained in 6.12.5.9.4 (Slave mode with automatic resynchronization).
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINS_DUM_EN : LIN Slave Divider Update Method Enable Bit\nNote2: This bit is used for LIN Slave Automatic Resynchronization mode. (for Non-Automatic Resynchronization mode, this bit should be kept cleared) \nNote3: The control and interactions of this field are explained in 6.12.5.9.4 (Slave mode with automatic resynchronization).
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_MUTE_EN : LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in LIN slave mode.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_SHD : LIN TX Send Header Enable Bit The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LIN_HEAD_SEL (UA_LIN_CTL[23:22]). Note1: These registers are shadow registers of LIN_TX_EN (UA_ALT_CSR[7]) user can read/write it by setting LIN_TX_EN (UA_ALT_CSR[7]) or LIN_SHD (UA_LIN_CTL[8]). Note2: When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LIN_HEAD_SEL (UA_LIN_CTL[23:22]) field) transfer operation finished, this bit will be cleared automatically.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_IDPEN : LIN ID Parity Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_BKDET_EN : LIN Break Detection Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_RX_DIS : LIN Receiver Disable Bit\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIT_ERR_EN : Bit Error Detect Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_BKFL : LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of LIN_BKFL (UA_ALT_CSR[19:16]), User can read/write it by setting LIN_BKFL (UA_ALT_CSR[3:0]) or LIN_BKFL (UA_LIN_CTL[19:16]).\nNote2: This break field length is LIN_BKFL + 1.\n
bits : 16 - 19 (4 bit)
access : read-write

LIN_BS_LEN : LIN Break/Sync Delimiter Length\n\nNote: This bit is used for LIN master to sending header field.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_HEAD_SEL : LIN Header Select\n
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_PID : LIN PID Register\nThis field contains the LIN frame ID value when in LIN function mode, the frame ID parity can be generated by software or hardware depends on LIN_IDPEN (UA_LIN_CTL[9]). \n\nNote1: User can filled any 8-bit value to this field and the bit 24 indicates ID0 (LSB first).\nNote2: This field can be used for LIN master mode or slave mode.
bits : 24 - 31 (8 bit)
access : read-write

LINS_HDET_F : LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINS_HERR_F : LIN Slave Header Error Flag This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it. The header errors include break delimiter is too short , frame error in sync field or Identifier field , sync field data is not 0x55 without automatic resynchronization mode , sync field deviation error with automatic resynchronization mode , sync field measure time-out with automatic resynchronization mode and LIN header reception time-out .
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINS_IDPERR_F : LIN Slave ID Parity Error Flag\nThis bit is set by hardware when receipted frame ID parity is not correct.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINS_SYNC_F : LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in automatic resynchronization mode. When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.\nNote2: This bit is cleared by writing 1 to it.\nNote3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_BKDET_F : LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIT_ERR_F : Bit Error Detect Status Flag\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F (UA_LIN_SR[9]) will be set.\n
bits : 9 - 9 (1 bit)
access : read-write

RDA_IEN : Receive Data Available Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THRE_IEN : Transmit Holding Register Empty Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLS_IEN : Receive Line Status Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEM_IEN : Modem Status Interrupt Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUT_IEN : RX Time Out Interrupt Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUF_ERR_IEN : Buffer Error Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_EN : UART Wake-up Function Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_IEN : LIN Bus Interrupt Enable Bit\nNote: This field is used for LIN function mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TIME_OUT_EN : Receive Buffer Time Out Counter Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_RTS_EN : nRTS Auto Flow Control Enable Bit\nWhen nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTS_TRI_LEV (UA_FCR[19:16]), the UART will de-assert nRTS signal.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CTS_EN : nCTS Auto Flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device until nCTS is asserted).
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFR : RX Field Software Reset\nWhen RFR is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TFR : TX Field Software Reset\nWhen TFR is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART engine clock cycles.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL, the RDA_IF will be set (if RDA_IEN(UA_IER [0]) enabled, and an interrupt will be generated).\n
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_DIS : Receiver Disable Register\nThe receiver is disabled or not (set 1 to disable receiver)\nNote: This field is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485_NMM (UA_ALT_CSR [8]) is programmed.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_TRI_LEV : nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WLS : Word Length Selection\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Number of STOP Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable Bit\nNote: This bit has effect only when PBE (UA_LCR[3]) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable Bit\nNote: If PBE (UA_LCR[3]) and EBE (UA_LCR[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UA_LCR[3]) is 1 and EBE (UA_LCR[4]) is 0 then the parity bit is transmitted and checked as 1.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.