\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x3C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : SPI Transfer Control Bit and Busy Status\nIf FIFO mode is disabled, during the data transfer, this bit keeps the value of 1. As the transfer is finished, this bit will be cleared automatically. Software can read this bit to check if the SPI is in busy status.\nIn FIFO mode, this bit will be controlled by hardware. Software should not modify this bit. In Slave mode, this bit always returns 1 when this register is read by software. In Master mode, this bit reflects the busy or idle status of SPI.\nNote:\nWhen FIFO mode is disabled, all configurations should be set before writing 1 to this GO_BUSY bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data transfer stopped
#1 : 1
In Master mode, writing 1 to this bit to start the SPI data transfer in Slave mode, writing 1 to this bit indicates that the slave is ready to communicate with a master
End of enumeration elements list.
RX_NEG : Receive on Negative Edge\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data input signal is latched on the rising-edge of SPI bus clock
#1 : 1
Received data input signal is latched on the falling-edge of SPI bus clock
End of enumeration elements list.
TX_NEG : Transmit on Negative Edge\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data output signal is changed on the rising-edge of SPI bus clock
#1 : 1
Transmitted data output signal is changed on the falling-edge of SPI bus clock
End of enumeration elements list.
TX_BIT_LEN : Transmit Bit Length\nThis field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits.\n
bits : 3 - 7 (5 bit)
access : read-write
LSB : Send LSB First\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#1 : 1
The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX)
End of enumeration elements list.
CLKP : Clock Polarity\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI bus clock is idle low
#1 : 1
SPI bus clock is idle high
End of enumeration elements list.
SP_CYCLE : Suspend Interval (Master Only)\nThe four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word. The default value is 0x3. The period of the suspend interval is obtained according to the following equation.\n (SP_CYCLE[3:0] + 0.5) * period of SPI clock cycle\nExample:\n
bits : 12 - 15 (4 bit)
access : read-write
IF : Unit Transfer Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
IE : Unit Transfer Interrupt Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI unit transfer interrupt Disabled
#1 : 1
SPI unit transfer interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Master mode
#1 : 1
Slave mode
End of enumeration elements list.
REORDER : Byte Reorder Function Enable Bit\nNote:\nByte reorder function is only available if TX_BIT_LEN is defined as 16, 24, and 32 bits.\nIn Slave mode with level-trigger configuration, the slave select pin must be kept at active state during the byte suspend interval.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Byte reorder function Disabled
#1 : 1
Byte reorder function Enabled. A byte suspend interval will be inserted among each byte. The period of the byte suspend interval depends on the setting of SP_CYCLE
End of enumeration elements list.
FIFO : FIFO Mode Enable Bit
Note:
Before enabling FIFO mode, the other related settings should be set in advance.
In Master mode, if the FIFO mode is enabled, the GO_BUSY bit will be set to 1 automatically after writing data to the transmit FIFO buffer the GO_BUSY bit will be cleared to 0 automatically when the SPI controller is in idle. If all data stored at transmit FIFO buffer are sent out, the TX_EMPTY bit will be set to 1 and the GO_BUSY bit will be cleared to 0.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO mode Disabled
#1 : 1
FIFO mode Enabled
End of enumeration elements list.
RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[24].\n
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RX_FULL : Receive FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[25].\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIOF buffer is not full
#1 : 1
Receive FIFO buffer is full
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_STAUTS[26].\n
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_STATUS[27].\n
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
Data Receive Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RX : Data Receive Register\nThe data receive register holds the datum received from SPI data input pin. If the FIFO mode is disabled, the software can access the last received data by reading this register. If the FIFO bit is set as 1 and the RX_EMPTY bit, SPI_CNTRL[24] or SPI_STATUS[24], is not set to 1, then the receive FIFO buffers can be accessed through software by reading this register. This is a read-only register.
bits : 0 - 31 (32 bit)
access : read-only
Data Transmit Register
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TX : Data Transmit Register\nThe Data Transmit Register holds the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field TX_BIT_LEN in the SPI_CNTRL register.\nFor example, if TX_BIT_LEN is set to 0x08, the bit field TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x00, the SPI controller will perform a 32-bit transfer.\nNote: When the SPI controller is configured as a slave device and FIFO mode is disabled, if the SPI controller attempts to transmit data to a master, the transmit data register should be updated by software before setting the GO_BUSY bit to 1
bits : 0 - 31 (32 bit)
access : write-only
Control and Status Register 2
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NOSLVSEL : Slave 3-wire Mode Enable Bit\n In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.\nNote: In Slave 3-wire mode, the SS_LTRIG (SPI_SSR[4]) will be set as 1 automatically.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
4-wire bi-direction interface in Slave mode
#1 : 1
3-wire bi-direction interface in Slave mode. The controller will be ready to transmit/receive data after the GO_BUSY bit is set to 1
End of enumeration elements list.
SLV_ABORT : Slave 3-wire Mode Abort Control\nIn normal operation, there is an interrupt event when the received data meet the required bits which defined in TX_BIT_LEN.\nIf the received bits are less than the requirement and there is no more SPI clock input over one transaction time in Slave 3-wire mode, user can set this bit to force the current transfer done and then user can get a transfer done interrupt event.\nNote: This bit will be cleared to 0 automatically by hardware after it is set to 1 by software..
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Force the current transaction done
End of enumeration elements list.
SSTA_INTEN : Slave 3-wire Mode Start Interrupt Enable Bit\nUsed to enable interrupt when the transfer has started in Slave 3-wire mode. If there is no transfer done interrupt over the time period which is defined by user after the transfer start, the user can set the SLV_ABORT bit to force the transfer done.\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transaction start interrupt Disabled
#1 : 1
Transaction start interrupt Enabled. It will be cleared to 0 as the current transfer is done or the SLV_START_INTSTS bit is cleared
End of enumeration elements list.
SLV_START_INTSTS : Slave 3-wire Mode Start Interrupt Status\nThis bit indicates if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_STATUS[11].\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1
#1 : 1
A transaction has started in Slave 3-wire mode. It will be cleared automatically when a transaction is done or by writing 1 to this bit
End of enumeration elements list.
SS_INT_OPT : Slave Select Inactive Interrupt Option \nThis setting is only available if the SPI controller is configured as level trigger slave device.\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
As the slave select signal goes to inactive level, the IF bit will NOT be set to 1
#1 : 1
As the slave select signal goes to inactive level, the IF bit will be set to 1
End of enumeration elements list.
Clock Divider Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER : Clock Divider 1 Register \nThe value in this field is the frequency divider for generating the SPI peripheral clock, fspi_eclk, and the SPI bus clock of SPI master. The frequency is obtained according to the following equation. \n\nwhere \n is the SPI peripheral clock source, which is defined in the CLKSEL1 register.
bits : 0 - 7 (8 bit)
access : read-write
SPI FIFO Control Register
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CLR : Clear Receive FIFO Buffer\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear receive FIFO buffer. The RX_FULL flag will be cleared to 0 and the RX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
End of enumeration elements list.
TX_CLR : Clear Transmit FIFO Buffer\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear transmit FIFO buffer. The TX_FULL flag will be cleared to 0 and the TX_EMPTY flag will be set to 1. This bit will be cleared to 0 by hardware after it is set to 1 by software
End of enumeration elements list.
RX_INTEN : Receive Threshold Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX threshold interrupt Disabled
#1 : 1
RX threshold interrupt Enabled
End of enumeration elements list.
TX_INTEN : Transmit Threshold Interrupt Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX threshold interrupt Disabled
#1 : 1
TX threshold interrupt Enabled
End of enumeration elements list.
RXOV_INTEN : Receive FIFO Overrun Interrupt Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO overrun interrupt Disabled
#1 : 1
Receive FIFO overrun interrupt Enabled
End of enumeration elements list.
TIMEOUT_INTEN : Receive FIFO Time-out Interrupt Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out interrupt Disabled
#1 : 1
Time-out interrupt Enabled
End of enumeration elements list.
RX_THRESHOLD : Receive FIFO Threshold\nIf the valid data count of the receive FIFO buffer is larger than the RX_THRESHOLD setting, the RX_INTSTS bit will be set to 1, else the RX_INTSTS bit will be cleared to 0.
bits : 24 - 26 (3 bit)
access : read-write
TX_THRESHOLD : Transmit FIFO Threshold\nIf the valid data count of the transmit FIFO buffer is less than or equal to the TX_THRESHOLD setting, the TX_INTSTS bit will be set to 1, else the TX_INTSTS bit will be cleared to 0.
bits : 28 - 30 (3 bit)
access : read-write
SPI Status Register
address_offset : 0x44 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_INTSTS : Receive FIFO Threshold Interrupt Status (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the receive FIFO buffer is less than or equal to the setting value of RX_THRESHOLD
#1 : 1
The valid data count within the receive FIFO buffer is larger than the setting value of RX_THRESHOLD
End of enumeration elements list.
RX_OVERRUN : Receive FIFO Overrun Status\nWhen the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.\nNote: This bit will be cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive FIFO does not overrun
#1 : 1
Receive FIFO overruns
End of enumeration elements list.
TX_INTSTS : Transmit FIFO Threshold Interrupt Status (Read Only)\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The valid data count within the transmit FIFO buffer is larger than the setting value of TX_THRESHOLD
#1 : 1
The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TX_THRESHOLD
End of enumeration elements list.
SLV_START_INTSTS : Slave Start Interrupt Status\nIt is used to dedicate if a transaction has started in Slave 3-wire mode. It is a mutual mirror bit of SPI_CNTRL2[11].\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave has not detected any SPI clock transition since the SSTA_INTEN bit was set to 1. The transfer is not started
#1 : 1
A transaction has started in Slave 3-wire mode. It will be cleared as a transaction is done or by writing 1 to this bit
End of enumeration elements list.
RX_FIFO_COUNT : Receive FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of receive FIFO buffer.
bits : 12 - 15 (4 bit)
access : read-only
IF : SPI Unit Transfer Interrupt Flag\nA mutual mirror bit of SPI_CNTRL[16].\nNote: This bit will be cleared by writing 1 to itself.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No transaction has been finished since this bit was cleared to 0
#1 : 1
SPI controller has finished one unit transfer
End of enumeration elements list.
TIMEOUT : Time-out Interrupt Flag\nNote: This bit will be cleared by writing 1 to itself.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No receive FIFO time-out event
#1 : 1
Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 SPI peripheral clock period in Slave mode. When the received FIFO buffer is read by software, the time-out status will be cleared automatically
End of enumeration elements list.
RX_EMPTY : Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[24].\n
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
RX_FULL : Receive FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[25].\n
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive FIFO buffer is not empty
#1 : 1
Receive FIFO buffer is empty
End of enumeration elements list.
TX_EMPTY : Transmit FIFO Buffer Empty Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[26].\n
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not empty
#1 : 1
Transmit FIFO buffer is empty
End of enumeration elements list.
TX_FULL : Transmit FIFO Buffer Full Indicator (Read Only)\nA mutual mirror bit of SPI_CNTRL[27].\n
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit FIFO buffer is not full
#1 : 1
Transmit FIFO buffer is full
End of enumeration elements list.
TX_FIFO_COUNT : Transmit FIFO Data Count (Read Only)\nThis bit field indicates the valid data count of transmit FIFO buffer.
bits : 28 - 31 (4 bit)
access : read-only
Slave Select Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSR : Slave Select Control Bits (Master Only)\nIf AUTOSS bit is cleared\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the SPIx_SS pin to inactive state.\nKeep the SPIx_SS pin to inactive state
#1 : 1
Set the SPIx_SS pin to active state.\nSelect the SPIx_SS pin to be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time. The active state of SPIx_SS is specified in SS_LVL
End of enumeration elements list.
SS_LVL : Slave Select Active Level\nThis bit defines the active status of slave select signal (SPI_SS).\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The slave select signal SPI_SS is active on low-level/falling-edge
#1 : 1
The slave select signal SPI_SS is active on high-level/rising-edge
End of enumeration elements list.
AUTOSS : Automatic Slave Select Function Enable Bit (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSR[0]
#1 : 1
If this bit is set, SPI_SS signals will be generated automatically by hardware. It means that device/slave select signal, which is set in SPI_SSR[0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished
End of enumeration elements list.
SS_LTRIG : Slave Select Level Trigger Enable Bit (Slave Only)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave select signal is edge-trigger. This is the default value. The SS_LVL bit decides the signal is active after a falling-edge or rising-edge
#1 : 1
Slave select signal is level-trigger. The SS_LVL bit decides the signal is active low or active high
End of enumeration elements list.
LTRIG_FLAG : Level Trigger Accomplish Flag\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done. \n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transferred bit length of one transaction does not meet the specified requirement
#1 : 1
Transferred bit length meets the specified requirement which defined in TX_BIT_LEN. Note: This bit is READ only. As the GO_BUSY bit is set to 1 by software, the LTRIG_FLAG will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period. In FIFO mode, this bit has no meaning
End of enumeration elements list.
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