Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x98 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA4 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x44 byte (0x0)
mem_usage : registers
protection : not protected
A/D Data Register 0 for SAMPLEA0
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSLT : A/D Conversion Result\nThis field contains 12-bit conversion result.
bits : 0 - 11 (12 bit)
access : read-only
OVERRUN : over Run Flag\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT[11:0] is the recent conversion result
#1 : 1
Data in RSLT[11:0] is overwritten. If converted data in RSLT[11:0] has not been read before new conversion result is loaded to this register, OVERRUN is set to 1. It is cleared by hardware after ADDR register is read
End of enumeration elements list.
VALID : Valid Flag\nThis bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after ADDR register is read.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RSLT[11:0] bits is not valid
#1 : 1
Data in RSLT[11:0] bits is valid
End of enumeration elements list.
A/D Data Register 4 for SAMPLEA4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register Double Buffer for SAMPLEA0
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSLTDB : A/D Conversion Result\n
bits : 0 - 11 (12 bit)
access : read-only
VALID : Valid Flag\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Double data in RSLTDB[11:0] bits is not valid
#1 : 1
Double data in RSLTDB[11:0] bits is valid
End of enumeration elements list.
A/D Data Register Double Buffer for SAMPLEA1
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register Double Buffer for SAMPLEA2
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register Double Buffer for SAMPLEA3
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register Double Buffer for SAMPLEB0
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register Double Buffer for SAMPLEB1
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register Double Buffer for SAMPLEB2
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register Double Buffer for SAMPLEB3
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Double Buffer Mode Select
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBMA0 : Double Buffer Mode for SAMPLE A0 \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SampleA0 has one sample result register. (default)
#1 : 1
SampleA0 has two sample result registers
End of enumeration elements list.
DBMA1 : Double Buffer Mode for SAMPLE A1 \n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SampleA1 has one sample result register. (default)
#1 : 1
SampleA1 has two sample result registers
End of enumeration elements list.
DBMA2 : Double Buffer Mode for SAMPLE A2 \n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SampleA2 has one sample result register. (default)
#1 : 1
SampleA2 has two sample result registers
End of enumeration elements list.
DBMA3 : Double Buffer Mode for SAMPLE A3 \n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SampleA3 has one sample result register. (default)
#1 : 1
SampleA3 has two sample result registers
End of enumeration elements list.
DBMB0 : Double Buffer Mode for SAMPLE B0 \n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
SampleB0 has one sample result register. (default)
#1 : 1
SampleB0 has two sample result registers
End of enumeration elements list.
DBMB1 : Double Buffer Mode for SAMPLE B1 \n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
SampleB1 has one sample result register. (default)
#1 : 1
SampleB1 has two sample result registers
End of enumeration elements list.
DBMB2 : Double Buffer Mode for SAMPLE B2 \n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
SampleB2 has one sample result register. (default)
#1 : 1
SampleB2 has two sample result registers
End of enumeration elements list.
DBMB3 : Double Buffer Mode for SAMPLE B3 \n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SampleB3 has one sample result register. (default)
#1 : 1
SampleB3 has two sample result registers
End of enumeration elements list.
A/D Interrupt 0 Source Enable Control Register.
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IESPLA0 : SAMPLE A0 Interrupt Mask Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE A0 interrupt mask Disabled
#1 : 1
SAMPLE A0 interrupt mask Enabled
End of enumeration elements list.
IESPLA1 : SAMPLE A1 Interrupt Mask Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE A1 interrupt mask Disabled
#1 : 1
SAMPLE A1 interrupt mask Enabled
End of enumeration elements list.
IESPLA2 : SAMPLE A2 Interrupt Mask Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE A2 interrupt mask Disabled
#1 : 1
SAMPLE A2 interrupt mask Enabled
End of enumeration elements list.
IESPLA3 : SAMPLE A3 Interrupt Mask Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE A3 interrupt mask Disabled
#1 : 1
SAMPLE A3 interrupt mask Enabled
End of enumeration elements list.
IESPLA4 : SAMPLE A4 Interrupt Mask Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE A4 interrupt mask Disabled
#1 : 1
SAMPLE A4 interrupt mask Enabled
End of enumeration elements list.
IESPLA5 : SAMPLE A5 Interrupt Mask Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE A5 interrupt mask Disabled
#1 : 1
SAMPLE A5 interrupt mask Enabled
End of enumeration elements list.
IESPLA6 : SAMPLE A6 Interrupt Mask Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE A6 interrupt mask Disabled
#1 : 1
SAMPLE A6 interrupt mask Enabled
End of enumeration elements list.
IESPLA7 : SAMPLE A7 Interrupt Mask Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE A7 interrupt mask Disabled
#1 : 1
SAMPLE A7 interrupt mask Enabled
End of enumeration elements list.
IESPLB0 : SAMPLE B0 Interrupt Mask Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE B0 interrupt mask Disabled
#1 : 1
SAMPLE B0 interrupt mask Enabled
End of enumeration elements list.
IESPLB1 : SAMPLE B1 Interrupt Mask Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE B1 interrupt mask Disabled
#1 : 1
SAMPLE B1 interrupt mask Enabled
End of enumeration elements list.
IESPLB2 : SAMPLE B2 Interrupt Mask Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE B2 interrupt mask Disabled
#1 : 1
SAMPLE B2 interrupt mask Enabled
End of enumeration elements list.
IESPLB3 : SAMPLE B3 Interrupt Mask Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE B3 interrupt mask Disabled
#1 : 1
SAMPLE B3 interrupt mask Enabled
End of enumeration elements list.
IESPLB4 : SAMPLE B4 Interrupt Mask Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE B4 interrupt mask Disabled
#1 : 1
SAMPLE B4 interrupt mask Enabled
End of enumeration elements list.
IESPLB5 : SAMPLE B5 Interrupt Mask Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE B5 interrupt mask Disabled
#1 : 1
SAMPLE B5 interrupt mask Enabled
End of enumeration elements list.
IESPLB6 : SAMPLE B6 Interrupt Mask Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE B6 interrupt mask Disabled
#1 : 1
SAMPLE B6 interrupt mask Enabled
End of enumeration elements list.
IESPLB7 : SAMPLE B7 Interrupt Mask Enable Bit\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLE B7 interrupt mask Disabled
#1 : 1
SAMPLE B7 interrupt mask Enabled
End of enumeration elements list.
A/D Interrupt 1 Source Enable Control Register.
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Interrupt 2 Source Enable Control Register.
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 5 for SAMPLEA5
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Interrupt 3 Source Enable Control Register.
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLEA0
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWM00REN : PWM0_CH0 Rising Edge Trigger Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH0 rising edge trigger Disabled
#1 : 1
PWM0_CH0 rising edge trigger Enabled
End of enumeration elements list.
PWM00FEN : PWM0_CH0 Falling Edge Trigger Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH0 falling edge trigger Disabled
#1 : 1
PWM0_CH0 falling edge trigger Enabled
End of enumeration elements list.
PWM00PEN : PWM0_CH0 Period Trigger Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH0 period trigger Disabled
#1 : 1
PWM0_CH0 period trigger Enabled
End of enumeration elements list.
PWM00CEN : PWM0_CH0 Center Trigger Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH0 center trigger Disabled
#1 : 1
PWM0_CH0 center trigger Enabled
End of enumeration elements list.
PWM02REN : PWM0_CH2 Rising Edge Trigger Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH2 rising edge trigger Disabled
#1 : 1
PWM0_CH2 rising edge trigger Enabled
End of enumeration elements list.
PWM02FEN : PWM0_CH2 Falling Edge Trigger Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH2 falling edge trigger Disabled
#1 : 1
PWM0_CH2 falling edge trigger Enabled
End of enumeration elements list.
PWM02PEN : PWM0_CH2 Period Trigger Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH2 period trigger Disabled
#1 : 1
PWM0_CH2 period trigger Enabled
End of enumeration elements list.
PWM02CEN : PWM0_CH2 Center Trigger Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH2 center trigger Disabled
#1 : 1
PWM0_CH2 center trigger Enabled
End of enumeration elements list.
PWM04REN : PWM0_CH4 Rising Edge Trigger Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH4 rising edge trigger Disabled
#1 : 1
PWM0_CH4 rising edge trigger Enabled
End of enumeration elements list.
PWM04FEN : PWM0_CH4 Falling Rdge Trigger Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH4 falling edge trigger Disabled
#1 : 1
PWM0_CH4 falling edge trigger Enabled
End of enumeration elements list.
PWM04PEN : PWM0_CH4 Period Trigger Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH4 period trigger Disabled
#1 : 1
PWM0_CH4 period trigger Enabled
End of enumeration elements list.
PWM04CEN : PWM0_CH4 Center Trigger Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0_CH4 center trigger Disabled
#1 : 1
PWM0_CH4 center trigger Enabled
End of enumeration elements list.
PWM10REN : PWM1_CH0 Rising Edge Trigger Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH0 rising edge trigger Disabled
#1 : 1
PWM1_CH0 rising edge trigger Enabled
End of enumeration elements list.
PWM10FEN : PWM1_CH0 Falling Edge Trigger Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH0 falling edge trigger Disabled
#1 : 1
PWM1_CH0 falling edge trigger Enabled
End of enumeration elements list.
PWM10PEN : PWM1_CH0 Period Trigger Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH0 period trigger Disabled
#1 : 1
PWM1_CH0 period trigger Enabled
End of enumeration elements list.
PWM10CEN : PWM1_CH0 Center Trigger Enable Bit\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH0 center trigger Disabled
#1 : 1
PWM1_CH0 center trigger Enabled
End of enumeration elements list.
PWM12REN : PWM1_CH2 Rising Edge Trigger Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH2 rising edge trigger Disabled
#1 : 1
PWM1_CH2 rising edge trigger Enabled
End of enumeration elements list.
PWM12FEN : PWM1_CH2 Falling Edge Trigger Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH2 falling edge trigger Disabled
#1 : 1
PWM1_CH2 falling edge trigger Enabled
End of enumeration elements list.
PWM12PEN : PWM1_CH2 Period Trigger Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH2 period trigger Disabled
#1 : 1
PWM1_CH2 period trigger Enabled
End of enumeration elements list.
PWM12CEN : PWM1_CH2 Center Trigger Enable Bit\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH2 center trigger Disabled
#1 : 1
PWM1_CH2 center trigger Enabled
End of enumeration elements list.
PWM14REN : PWM1_CH4 Rising Edge Trigger Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH4 rising edge trigger Disabled
#1 : 1
PWM1_CH4 rising edge trigger Enabled
End of enumeration elements list.
PWM14FEN : PWM1_CH4 Falling Edge Trigger Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH4 falling edge trigger Disabled
#1 : 1
PWM1_CH4 falling edge trigger Enabled
End of enumeration elements list.
PWM14PEN : PWM1_CH4 Period Trigger Enable Bit\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH4 period trigger Disabled
#1 : 1
PWM1_CH4 period trigger Enabled
End of enumeration elements list.
PWM14CEN : PWM1_CH4 Center Trigger Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM1_CH4 center trigger Disabled
#1 : 1
PWM1_CH4 center trigger Enabled
End of enumeration elements list.
PWM20REN : BPWM0_CH0 Rising Edge Trigger Enable Bit\n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0_CH0 rising edge trigger Disabled
#1 : 1
BPWM0_CH0 rising edge trigger Enabled
End of enumeration elements list.
PWM20FEN : BPWM0_CH0 Falling Edge Trigger Enable Bit\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0_CH0 falling edge trigger Disabled
#1 : 1
BPWM0_CH0 falling edge trigger Enabled
End of enumeration elements list.
PWM20PEN : BPWM0_CH0 Period Trigger Enable Bit\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0_CH0 period trigger Disabled
#1 : 1
BPWM0_CH0 period trigger Enabled
End of enumeration elements list.
PWM20CEN : BPWM0_CH0 Center Trigger Enable Bit\n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0_CH0 center trigger Disabled
#1 : 1
BPWM0_CH0 center trigger Enabled
End of enumeration elements list.
PWM21REN : BPWM0_CH1 Rising Edge Trigger Enable Bit\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0_CH1 rising edge trigger Disabled
#1 : 1
BPWM0_CH1 rising edge trigger Enabled
End of enumeration elements list.
PWM21FEN : BPWM0_CH1 Falling Edge Trigger Enable Bit\n
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0_CH1 falling edge trigger Disabled
#1 : 1
BPWM0_CH1 falling edge trigger Enabled
End of enumeration elements list.
PWM21PEN : BPWM0_CH1 Period Trigger Enable Bit\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0_CH1 period trigger Disabled
#1 : 1
BPWM0_CH1 period trigger Enabled
End of enumeration elements list.
PWM21CEN : BPWM0_CH1 Center Trigger Enable Bit\n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
BPWM0_CH1 center trigger Disabled
#1 : 1
BPWM0_CH1 center trigger Enabled
End of enumeration elements list.
A/D Trigger Condition for SAMPLEA1
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLEA2
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLEA3
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLEB0
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLEB1
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLEB2
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Trigger Condition for SAMPLEB3
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 6 for SAMPLEA6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 7 for SAMPLEA7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 8 for SAMPLEB0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 9 for SAMPLEB1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 10 for SAMPLEB2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 11 for SAMPLEB3
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 12 for SAMPLEB4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 13 for SAMPLEB5
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 14 for SAMPLEB6
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 15 for SAMPLEB7
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 1 for SAMPLEA1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AD_EN : A/D Converter Enable Bit\nNote: Before starting the A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter Disabled
#1 : 1
A/D converter Enabled
End of enumeration elements list.
ADRESET : ADCA, ADCB A/D Converter Control Circuits Reset\nNote: This bit remains 1 during ADC reset, when ADC reset end, the ADRESET bit is automatically cleared to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 has no effect
#1 : 1
Writing 1 will cause ADC control circuits reset to initial state, but not change the ADC registers value
End of enumeration elements list.
ADIE0 : Specific SAMPLE A/D ADINT0 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF0 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE0 bit is set then conversion end interrupt request ADINT0 is generated.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific SAMPLE A/D ADINT0 interrupt function Disabled
#1 : 1
Specific SAMPLE A/D ADINT0 interrupt function Enabled
End of enumeration elements list.
ADIE1 : Specific SAMPLE A/D ADINT1 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF1 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE1 bit is set then conversion end interrupt request ADINT1 is generated.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific SAMPLE A/D ADINT1 interrupt function Disabled
#1 : 1
Specific SAMPLE A/D ADINT1 interrupt function Enabled
End of enumeration elements list.
ADIE2 : Specific SAMPLE A/D ADINT2 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF2 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE2 bit is set then conversion end interrupt request ADINT2 is generated.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific SAMPLE A/D ADINT2 interrupt function Disabled
#1 : 1
Specific SAMPLE A/D ADINT2 interrupt function Enabled
End of enumeration elements list.
ADIE3 : Specific SAMPLE A/D ADINT3 Interrupt Enable Bit\nThe A/D converter generates a conversion end ADF3 flag in ADSR1 register upon the end of specific SAMPLE A/D conversion. If ADIE3 bit is set then conversion end interrupt request ADINT3 is generated.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific SAMPLE A/D ADINT3 interrupt function Disabled
#1 : 1
Specific SAMPLE A/D ADINT3 interrupt function Enabled
End of enumeration elements list.
A/D Channel Input Sources Select Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AINA0SEL : A/D Channel AINA[0] Analog Input Selection \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
AINA[0] pin P6.0/EADC0_CH0is selected as the ADC AINA[0] input signal
#1 : 1
OP Amplifier 0 output is selected as the ADC AINA[0] input signal
End of enumeration elements list.
AINB0SEL : A/D Channel AINB[0] Analog Input Selection\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
AINB[0] pin P7.0E/EADC1_CH0 is selected as the A/D AINB[0] input signal
#1 : 1
OP Amplifier 1 output is selected as the A/D AINB[0] input signal
End of enumeration elements list.
PRESEL : A/D Channel AINA[7] Analog Input Selection\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Analog Input Channel AINA7
#01 : 1
Band-gap (VBG) Analog Input
#10 : 2
VTEMP Internal Temperature Sensor Analog Input
#11 : 3
Analog ground
End of enumeration elements list.
A/D SAMPLE Software Start Register
address_offset : 0x48 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ADST7_0 : A/D SAMPLEA7~0 Software Force to Start ADC Conversion Register \n
bits : 0 - 7 (8 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Cause an ADC conversion when the priority is given to SAMPLEA
End of enumeration elements list.
ADST15_8 : A/D SAMPLEB7~0 Software Force to Start ADC Conversion Register \n
bits : 8 - 15 (8 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Cause an ADC conversion when the priority is given to SAMPLEB
End of enumeration elements list.
A/D SAMPLE Start of Conversion Pending Flag Register
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STPF7_0 : A/D SAMPLEA7~0 Start Conversion Pending Flag \n
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
0 : 0
There is no pending conversion for SAMPLEA
1 : 1
SAMPLEAn ADC start of conversion is pending
End of enumeration elements list.
STPF15_8 : A/D SAMPLEB7~0 Start Conversion Pending Flag \n
bits : 8 - 15 (8 bit)
access : read-only
Enumeration:
0 : 0
No pending conversion for SAMPLEB
1 : 1
SAMPLEBn ADC start of conversion is pending
End of enumeration elements list.
A/D ADINT3~0 Interrupt Flag over Run Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADFOV0 : A/D ADINT0 Interrupt Flag over Run Bit
Note: This bit is cleared by writing 1 to 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT0 interrupt flag is not over run
#1 : 1
ADINT0 interrupt flag is overwrite to 1
End of enumeration elements list.
ADFOV1 : A/D ADINT1 Interrupt Flag over Run Bit
Note: This bit is cleared by writing 1 to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT1 interrupt flag is not over run
#1 : 1
ADINT1 interrupt flag is overwrite to 1
End of enumeration elements list.
ADFOV2 : A/D ADINT2 Interrupt Flag over Run Bit
Note: This bit is cleared by writing 1 to 1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT2 interrupt flag is not over run
#1 : 1
ADINT2 interrupt flag is overwrite to 1
End of enumeration elements list.
ADFOV3 : A/D ADINT3 Interrupt Flag over Run Bit
Note: This bit is cleared by writing 1 to 1.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT3 interrupt flag is not over run
#1 : 1
ADINT3 interrupt pulse received when ADF3 is 1
End of enumeration elements list.
A/D SAMPLE Start of Conversion over Run Flag Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPOVF7_0 : A/D SAMPLEA7~SAMPLEA0 Start Conversion Overrun Flag\n
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
No SAMPLE event overrun
1 : 1
Indicates new SAMPLEAn event is generated while an old one event is pending
End of enumeration elements list.
SPOVF15_8 : A/D SAMPLEB7~SAMPLEB0 Start Conversion Overrun Flag\n
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0 : 0
No SAMPLE event overrun
1 : 1
Indicates new SAMPLEBn event is generated while an old one event is pending
End of enumeration elements list.
A/D SAMPLEA0 Control Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL : A/D SAMPLEA,B Channel Selection\n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
AINx[0]
#001 : 1
AINx[1]
#010 : 2
AINx[2]
#011 : 3
AINx[3]
#100 : 4
AINx[4]
#101 : 5
AINx[5]
#110 : 6
AINx[6]
#111 : 7
AINx[7]
End of enumeration elements list.
TRGSEL : A/D SAMPLE Start Conversion Trigger Source Selection\n
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Disable hardware trigger
#0001 : 1
External trigger from STADC pin input
#0010 : 2
ADC ADINT0 interrupt EOC pulse trigger
#0011 : 3
ADC ADINT1 interrupt EOC pulse trigger
#0100 : 4
Timer0 overflow pulse trigger
#0101 : 5
Timer1 overflow pulse trigger
#0110 : 6
Timer2 overflow pulse trigger
#0111 : 7
Timer3 overflow pulse trigger
#1000 : 8
PWM00 trigger
#1001 : 9
PWM02 trigger
#1010 : 10
PWM04 trigger
#1011 : 11
PWM10 trigger
#1100 : 12
PWM12 trigger
#1101 : 13
PWM14 trigger
#1110 : 14
PWM20 trigger
#1111 : 15
PWM21 trigger
End of enumeration elements list.
TRGDLYCNT : A/D SAMPLE Start Conversion Trigger Delay Time\n
bits : 8 - 15 (8 bit)
access : read-write
TRGDLYDIV : A/D SAMPLE Start Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
ADC_CLK/1
#01 : 1
ADC_CLK/2
#10 : 2
ADC_CLK/4
#11 : 3
ADC_CLK/16
End of enumeration elements list.
EXTREN : A/D External Trigger Rising Edge Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising edge Disabled when A/D selects STADC as trigger source
#1 : 1
Rising edge Enabled when A/D selects STADC as trigger source
End of enumeration elements list.
EXTFEN : A/D External Trigger Falling Edge Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge Disabled when A/D selects STADC as trigger source
#1 : 1
Falling edge Enabled when A/D selects STADC as trigger source
End of enumeration elements list.
A/D SAMPLEA1 Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEA2 Control Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEA3 Control Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEA4 Control Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL : A/D SAMPLEA,B Channel Selection\n
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
AINx[0]
#001 : 1
AINx[1]
#010 : 2
AINx[2]
#011 : 3
AINx[3]
#100 : 4
AINx[4]
#101 : 5
AINx[5]
#110 : 6
AINx[6]
#111 : 7
AINx[7]
End of enumeration elements list.
TRGSEL : A/D SAMPLE Start Conversion Trigger Source Selection\n
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#000 : 0
Disable hardware trigger
#001 : 1
External trigger from STADC pin input
#010 : 2
ADC ADINT0 interrupt EOC pulse trigger
#011 : 3
ADC ADINT1 interrupt EOC pulse trigger
#100 : 4
Timer0 overflow pulse trigger
#101 : 5
Timer1 overflow pulse trigger
#110 : 6
Timer2 overflow pulse trigger
#111 : 7
Timer3 overflow pulse trigger
End of enumeration elements list.
EXTREN : A/D External Trigger Rising Edge Enable Bit\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising edge Disabled when A/D selects STADC as trigger source
#1 : 1
Rising edge Enabled when A/D selects STADC as trigger source
End of enumeration elements list.
EXTFEN : A/D External Trigger Falling Edge Enable Bit\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge Disabled when A/D selects STADC as trigger source
#1 : 1
Falling edge Enabled when A/D selects STADC as trigger source
End of enumeration elements list.
A/D SAMPLEA5 Control Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEA6 Control Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEA7 Control Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEB0 Control Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEB1 Control Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 2 for SAMPLEA2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEB2 Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEB3 Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEB4 Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEB5 Control Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEB6 Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLEB7 Control Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D SAMPLE Simultaneous Mode Select Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIMUSEL0 : A/D SAMPLEA0, SAMPLEB0 Simultaneous Sampling Mode Selection \n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLEA0, SAMPLEB0 are in single sampling mode, both SAMPLEA0 and SAMPLEB0's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLEA0, SAMPLEB0 are in simultaneous sampling mode, Only SAMPLEA0 can trigger both the ADC conversions of SAMPLEA0 and SAMPLEB0, SAMPLEB0 trigger select TRGSEL is ignored. If SAMPLEA0's CHSEL = 1, and SAMPLEB0's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
End of enumeration elements list.
SIMUSEL1 : A/D SAMPLEA1, SAMPLEB1 Simultaneous Sampling Mode Selection \n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLEA1, SAMPLEB1 are in single sampling mode, both SAMPLEA1 and SAMPLEB1's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLEA1, SAMPLEB1 are in simultaneous sampling mode, Only SAMPLEA1 can trigger both the ADC conversions of SAMPLEA1 and SAMPLEB1, SAMPLEB1 trigger select TRGSEL is ignored. If SAMPLEA1's CHSEL = 1, and SAMPLEB1's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
End of enumeration elements list.
SIMUSEL2 : A/D SAMPLEA2, SAMPLEB2 Simultaneous Sampling Mode Selection \n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLEA2, SAMPLEB2 are in single sampling mode, both SAMPLEA2 and SAMPLEB2's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLEA2, SAMPLEB2 are in simultaneous sampling mode, Only SAMPLEA2 can trigger both the ADC conversions of SAMPLEA2 and SAMPLEB2, SAMPLEB2 trigger select TRGSEL is ignored. If SAMPLEA2's CHSEL = 1, and SAMPLEB2's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
End of enumeration elements list.
SIMUSEL3 : A/D SAMPLEA3, SAMPLEB3 Simultaneous Sampling Mode Select Ion\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLEA3, SAMPLEB3 are in single sampling mode, both SAMPLEA3 and SAMPLEB3's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLEA3, SAMPLEB3 are in simultaneous sampling mode, Only SAMPLEA3 can trigger both the ADC conversions of SAMPLEA3 and SAMPLEB3, SAMPLEB3 trigger select TRGSEL is ignored. If SAMPLEA3's CHSEL = 1, and SAMPLEB3's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
End of enumeration elements list.
SIMUSEL4 : A/D SAMPLEA4, SAMPLEB4 Simultaneous Sampling Mode Select Ion\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLEA4, SAMPLEB4 are in single sampling mode, both SAMPLEA4 and SAMPLEB4's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLEA4, SAMPLEB4 are in simultaneous sampling mode, Only SAMPLEA4 can trigger both the ADC conversions of SAMPLEA4 and SAMPLEB4, SAMPLEB4 trigger select TRGSEL is ignored. If SAMPLEA4's CHSEL = 1, and SAMPLEB4's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
End of enumeration elements list.
SIMUSEL5 : A/D SAMPLEA5, SAMPLEB5 Simultaneous Sampling Mode Selection \n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLEA5, SAMPLEB5 are in single sampling mode, both SAMPLEA5 and SAMPLEB5's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLEA5, SAMPLEB5 are in simultaneous sampling mode, Only SAMPLEA5 can trigger both the ADC conversions of SAMPLEA5 and SAMPLEB5, SAMPLEB5 trigger select TRGSEL is ignored. If SAMPLEA5's CHSEL = 1, and SAMPLEB5's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
End of enumeration elements list.
SIMUSEL6 : A/D SAMPLEA6, SAMPLEB6 Simultaneous Sampling Mode Selection \n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLEA6, SAMPLEB6 are in single sampling mode, both SAMPLEA6 and SAMPLEB6's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLEA6, SAMPLEB6 are in simultaneous sampling mode, Only SAMPLEA6 can trigger both the ADC conversions of SAMPLEA6 and SAMPLEB6, SAMPLEB6 trigger select TRGSEL is ignored. If SAMPLEA6's CHSEL = 1, and SAMPLEB6's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
End of enumeration elements list.
SIMUSEL7 : A/D SAMPLEA7, SAMPLEB7 Simultaneous Sampling Mode Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SAMPLEA7, SAMPLEB7 are in single sampling mode, both SAMPLEA7 and SAMPLEB7's 3 bits of CHSEL define the ADC channels to be converted
#1 : 1
SAMPLEA7, SAMPLEB7 are in simultaneous sampling mode, Only SAMPLEA7 can trigger both the ADC conversions of SAMPLEA7 and SAMPLEB7, SAMPLEB7 trigger select TRGSEL is ignored. If SAMPLEA7's CHSEL = 1, SAMPLEB7's CHSEL = 3, the pair of channels are AINA[1], AINB[3], they will do the ADC conversion at the same time
End of enumeration elements list.
A/D Result Compare Register 0
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMP_EN : A/D Result Compare Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare Disabled
#1 : 1
Compare Enabled
End of enumeration elements list.
ADCMPIE : A/D Result Compare Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD(ADCMPRn[27:16], n=0, 1), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD(ADCMPRn[27:16] , n=0, 1), the internal match counter will increase one
End of enumeration elements list.
CMPSMPL : Compare SAMPLE Selection\n
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
SAMPLEA0 conversion result ADDRA0 is selected to be compared
#001 : 1
SAMPLEA1 conversion result ADDRA1 is selected to be compared
#010 : 2
SAMPLEA2 conversion result ADDRA2 is selected to be compared
#011 : 3
SAMPLEA3 conversion result ADDRA3 is selected to be compared
#100 : 4
SAMPLEB0 conversion result ADDRB0 is selected to be compared
#101 : 5
SAMPLEB1 conversion result ADDRB1 is selected to be compared
#110 : 6
SAMPLEB2 conversion result ADDRB2 is selected to be compared
#111 : 7
SAMPLEB3 conversion result ADDRB3 is selected to be compared
End of enumeration elements list.
CMPMATCNT : Compare Match Count\n
bits : 8 - 11 (4 bit)
access : read-write
CMPD : Comparison Data\nThe 12 bits data is used to compare with the conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage transition without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write
A/D Result Compare Register 1
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Status Register 0
address_offset : 0xB0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID7_0 : ADDRA7~0 Data Valid Flag\n
bits : 0 - 7 (8 bit)
access : read-only
VALID15_8 : ADDRB7~0 Data Valid Flag\n
bits : 8 - 15 (8 bit)
access : read-only
OVERRUN26_16 : ADDRA7~0 over Run Flag\n
bits : 16 - 23 (8 bit)
access : read-only
OVERRUN31_24 : ADDRB7~0 over Run Flag\n
bits : 24 - 31 (8 bit)
access : read-only
A/D Status Register 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADF0 : A/D ADINT0 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT0 interrupt pulse received
#1 : 1
ADINT0 interrupt pulse received
End of enumeration elements list.
ADF1 : A/D ADINT1 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
no ADINT1 interrupt pulse received
#1 : 1
ADINT1 interrupt pulse has been received
End of enumeration elements list.
ADF2 : A/D ADINT2 Interrupt Flag\nNote1: It is cleared by writing 1. \nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT2 interrupt pulse received
#1 : 1
ADINT2 interrupt pulse received
End of enumeration elements list.
ADF3 : A/D ADINT3 Interrupt Flag\nNote1: It is cleared by writing 1.\nNote2: This bit indicates whether an A/D conversion of specific SAMPLE has been completed
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT3 interrupt pulse received
#1 : 1
ADINT3 interrupt pulse received
End of enumeration elements list.
ADCMPO0 : ADC Compare 0 Output Status Bit
The 12 bits compare0 data CMPD(ADCMPR0[27:16]) is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage status.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR is less than CMPD(ADCMPR0[27:16]) setting
#1 : 1
Conversion result in ADDR is great than or equal CMPD(ADCMPR0[27:16]) setting
End of enumeration elements list.
ADCMPO1 : ADC Compare 1 Output Status Bit
The 12 bits compare1 data CMPD(ADCMPR1[27:16]) is used to compare with conversion result of specified SAMPLE. Software can use it to monitor the external analog input pin voltage status.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR less than CMPD(ADCMPR1[27:16]) setting
#1 : 1
Conversion result in ADDR great than or equal CMPD(ADCMPR1[27:16]) setting
End of enumeration elements list.
ADCMPF0 : ADC Compare 0 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by write 1.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet ADCMPR0 register setting
#1 : 1
Conversion result in ADDR meets ADCMPR0 register setting
End of enumeration elements list.
ADCMPF1 : ADC Compare 1 Flag\nWhen the specific SAMPLE A/D conversion result meets setting condition in ADCMPR1 register then this bit is set to 1. And it is cleared by write 1.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADDR does not meet ADCMPR1 register setting
#1 : 1
Conversion result in ADDR meets ADCMPR1 register setting
End of enumeration elements list.
BUSYA : BUSY/IDLE (Read Only)\n
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
A/D converter A (ADCA) is in idle state
#1 : 1
A/D converter A (ADCA) is busy at conversion
End of enumeration elements list.
CHANNELA : Current Conversion Channel (Read Only)\n
bits : 12 - 14 (3 bit)
access : read-only
Enumeration:
#000 : 0
AINA[0]
#001 : 1
AINA[1]
#010 : 2
AINA[2]
#011 : 3
AINA[3]
#100 : 4
AINA[4]
#101 : 5
AINA[5]
#110 : 6
AINA[6]
#111 : 7
AINA[7]
End of enumeration elements list.
BUSYB : BUSY/IDLE (Read Only)\n
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
A/D converter B (ADCB) is in idle state
#1 : 1
A/D converter B (ADCB) is busy at conversion
End of enumeration elements list.
CHANNELB : Current Conversion Channel (Read Only)\n
bits : 20 - 22 (3 bit)
access : read-only
Enumeration:
#000 : 0
AINB[0]
#001 : 1
AINB[1]
#010 : 2
AINB[2]
#011 : 3
AINB[3]
#100 : 4
AINB[4]
#101 : 5
AINB[5]
#110 : 6
AINB[6]
#111 : 7
AINB[7]
End of enumeration elements list.
AADFOV : All A/D Interrupt Flag over Run Bits Check \n
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of ADINT interrupt flag ADFOVn is overwritten to 1
#1 : 1
Any one of ADINT interrupt flag ADFOVn is overwritten to 1
End of enumeration elements list.
ASPOVF : All A/D SAMPLE Start Conversion over Run Flags Check\n
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of SAMPLE event over run flag SPOVFn is set to 1
#1 : 1
Any one of SAMPLE event over run flag SPOVFn is set to 1
End of enumeration elements list.
AVALID : All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of SAMPLE data register valid flag VALIDn is set to 1
#1 : 1
Any one of SAMPLE data register valid flag VALIDn is set to 1
End of enumeration elements list.
AOVERRUN : All SAMPLE A/D Result Data Register over Run Flags Check \n
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
None of SAMPLE data register over run flag OVERRUNn is set to 1
#1 : 1
Any one of SAMPLE data register over run flag OVERRUNn is set to 1
End of enumeration elements list.
A/D Timing Control Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADAEST : ADCA Extend Sampling Time \nWhen A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, User can extend A/D sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock.
bits : 0 - 7 (8 bit)
access : read-write
ADBEST : ADCB Extend Sampling Time \nWhen A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, User can extend A/D sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 ADC clock.
bits : 16 - 23 (8 bit)
access : read-write
A/D Data Register 3 for SAMPLEA3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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