SYST_CSR

NVIC_ISER

SYST_RVR

SYST_CVR

NVIC_ICER

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

NVIC_IPR5

NVIC_IPR6

NVIC_IPR7

CPUID

ICSR

AIRCR

SCR

SHPR2

SHPR3

ENABLE : None
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKINT : None
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSRC : None
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COUNTFLAG : Returns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-write

SETENA : Enable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). \nWriting 1 will enable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write

RELOAD : Value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write

CURRENT : Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (see SysTick Reload Value register).
bits : 0 - 23 (24 bit)
access : read-write

CLRENA : Disable one or more interrupts within a group of 32. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47). \nWriting 1 will disable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write

SETPEND : Writing 1 to a bit to set pending state of the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write

CLRPEND : Writing 1 to a bit un-pends the associated interrupt under software control. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write

PRI_0 : Priority of IRQ0 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_1 : Priority of IRQ1 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_2 : Priority of IRQ2 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_3 : Priority of IRQ3 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_4 : Priority of IRQ4 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_5 : Priority of IRQ5 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_6 : Priority of IRQ6 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_7 : Priority of IRQ7 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_8 : Priority of IRQ8 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_9 : Priority of IRQ9 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_10 : Priority of IRQ10 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_11 : Priority of IRQ11 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_12 : Priority of IRQ12 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_13 : Priority of IRQ13 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_14 : Priority of IRQ14 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of IRQ15 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_16 : Priority of IRQ16 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_17 : Priority of IRQ17 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_18 : Priority of IRQ18 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_19 : Priority of IRQ19 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_20 : Priority of IRQ20 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_21 : Priority of IRQ21 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_22 : Priority of IRQ22 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_23 : Priority of IRQ23 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_24 : Priority of IRQ24 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_25 : Priority of IRQ25 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_26 : Priority of IRQ26 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_27 : Priority of IRQ27 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_28 : Priority of IRQ28 0 denotes the highest priority and 3 denotes lowest priority
bits : 6 - 7 (2 bit)
access : read-write

PRI_29 : Priority of IRQ29 0 denotes the highest priority and 3 denotes lowest priority
bits : 14 - 15 (2 bit)
access : read-write

PRI_30 : Priority of IRQ30 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_31 : Priority of IRQ31 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

REVISION : Reads as 0x0
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Reads as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only

PART : Reads as 0xC for ARMv6-M parts
bits : 16 - 19 (4 bit)
access : read-only

IMPLEMENTER : None
bits : 24 - 31 (8 bit)
access : read-only

VECTACTIVE : Contains the active exception number\n
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTPENDING : Indicates the exception number of the highest priority pending enabled exception:\n
bits : 12 - 17 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRPENDING : Interrupt pending flag, excluding NMI and Faults:\nThis is a read only bit.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRPREEMPT : If set, a pending exception will be serviced on exit from the debug halt state.\nThis is a read only bit.
bits : 23 - 23 (1 bit)
access : read-write

PENDSTCLR : SysTick exception clear-pending bit.\nWrite:\nThis is a write only bit. On a register read its value is Unknown.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSTSET : SysTick exception set-pending bit.\nWrite:\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVCLR : PendSV clear-pending bit.\nWrite:\nThis is a write only bit.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PENDSVSET : PendSV set-pending bit.\nWrite:\nWriting 1 to this bit is the only way to set the PendSV exception state to pending.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NMIPENDSET : NMI set-pending bit\nWrite:\nBecause NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTCLRACTIVE : Set this bit to 1 will clears all active state information for fixed and configurable exceptions.\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write

SYSRESETREQ : Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write

VECTORKEY : When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
bits : 16 - 31 (16 bit)
access : read-write

SLEEPONEXIT : Indicates sleep-on-exit when returning from Handler mode to Thread mode:\nSetting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEPDEEP : Controls whether the processor uses sleep or deep sleep as its low power mode:\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEVONPEND : Send Event on Pending bit:\nWhen an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRI_11 : Priority of system handler 11 - SVCall 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority of system handler 14 - PendSV 0 denotes the highest priority and 3 denotes lowest priority
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority of system handler 15 - SysTick 0 denotes the highest priority and 3 denotes lowest priority
bits : 30 - 31 (2 bit)
access : read-write